Home
last modified time | relevance | path

Searched +full:drm +full:- +full:shim (Results 1 – 25 of 50) sorted by relevance

12

/third_party/mesa3d/docs/drivers/
Dpanfrost.rst6 on Mali-G52 and Mali-G57 but **non-conformant** on other GPUs. The following
34 --------
36 Panfrost's OpenGL support is a Gallium driver. Since Mali GPUs are 3D-only and
45 Build like ``meson . build/ -Ddri-drivers= -Dvulkan-drivers=
46 -Dgallium-drivers=panfrost -Dllvm=disabled`` for a build directory
53 ----
59 drm-shim chapter
60 --------
62 Panfrost implements ``drm-shim``, stubbing out the Panfrost kernel interface.
65 - Future hardware bring up
[all …]
Dv3d.rst6 <https://www.khronos.org/conformance/adopters/conformant-products/opengles#submission_882>`__
11 <https://www.kernel.org/doc/html/latest/gpu/v3d.html>`__ kernel DRM
13 4, the kernel uses the vc4 DRM driver for display support, so Mesa
15 behind-the-scenes buffer management between the two kernel drivers,
26 ----------------------
43 (``src/broadcom/drm-shim/``) to use simpenrose from an x86 system with
/third_party/mesa3d/src/drm-shim/
DREADME.md1 # DRM shim - Fake GEM kernel drivers in userspace for CI
4 be able to present either no-op GEM devices (for shader-db runs) or
5 simulator-backed GEM devices (for testing against a software simulator
11 - Doesn't know how to handle DRM fds getting passed over the wire from
13 - libc interception is rather glibc-specific and fragile.
14 - Can easily break gdb if the libc interceptor code is what's broken.
15 (ulimit -c unlimited and doing gdb on the core after the fact can
20 You choose the backend by setting `LD_PRELOAD` to the shim you want.
21 Since this will effectively fake another DRM device to your system,
23 to use it if it's not the only DRM device present. Setting
[all …]
Ddevice.c27 * wrappers, and calls into the driver-specific code as necessary.
40 #include "drm-uapi/drm.h"
57 /* Global state for the shim shared between libc, core, and driver. */
75 * Called when the first libc shim is called, to initialize GEM simulation
89 shim_device.mem_fd = memfd_create("shim mem", MFD_CLOEXEC); in drm_shim_device_init()
90 assert(shim_device.mem_fd != -1); in drm_shim_device_init()
102 * are offsets are page-size aligned as required. Otherwise, mmap will fail in drm_shim_device_init()
109 SHIM_MEM_SIZE - shim_page_size); in drm_shim_device_init()
119 shim_fd->fd = fd; in drm_shim_file_create()
120 p_atomic_set(&shim_fd->refcount, 1); in drm_shim_file_create()
[all …]
Ddrm_shim.c27 * Implements wrappers of libc functions to fake having a DRM device that
49 #include <drm-uapi/drm.h>
103 int render_node_minor = -1;
138 stat(render_node_path, &st) == -1) { in get_dri_render_node_minor()
172 override->path = path; in drm_shim_override_file()
173 override->contents = strdup(contents); in drm_shim_override_file()
186 * that might need to be wrapped with the shim.
237 fprintf(stderr, "Initializing DRM shim on %s\n", in init_shim()
314 if (render_node_minor == -1) in __xstat()
322 "/sys/dev/char/%d:%d/device/drm", in __xstat()
[all …]
/third_party/mesa3d/src/etnaviv/
Dmeson.build23 subdir('drm') subdir
25 if with_tools.contains('drm-shim')
26 subdir('drm-shim') subdir
/third_party/mesa3d/.gitlab-ci/
Drun-shader-db.sh1 set -e
2 set -v
4 ARTIFACTSDIR=`pwd`/shader-db
5 mkdir -p $ARTIFACTSDIR
11 cd /usr/local/shader-db
14 echo "Running drm-shim for $driver"
16 ./run -j${FDO_CI_CONCURRENT:-4} ./shaders \
17 > $ARTIFACTSDIR/${driver}-shader-db.txt
20 # Run shader-db over a number of supported chipsets for nouveau
22 echo "Running drm-shim for nouveau - $chipset"
[all …]
/third_party/mesa3d/src/freedreno/
Dmeson.build28 # TODO: use multi-argument dependency() in meson 0.60
37 dep_libxml2 = dependency('libxml-2.0', required: false)
46 subdir('drm') subdir
64 if with_tools.contains('drm-shim')
65 subdir('drm-shim') subdir
/third_party/mesa3d/src/nouveau/
Dmeson.build21 if with_tools.contains('drm-shim')
22 subdir('drm-shim') subdir
/third_party/mesa3d/src/amd/
Dmeson.build38 if with_tools.contains('drm-shim')
39 subdir('drm-shim') subdir
/third_party/mesa3d/src/panfrost/
Dmeson.build78 if with_tools.contains('drm-shim')
79 subdir('drm-shim') subdir
/third_party/libdrm/freedreno/kgsl/
DREADME2 in libdrm freedreno (before the upstream drm/msm driver). Note
3 that the kgsl backend requires the "kgsl-drm" shim driver, which
9 ----------------
12 DRM interface for GEM, which is basically sufficient to have DRI2
14 cores is via different other devices (/dev/kgsl-*). This is not
15 quite how I'd write a DRM driver, but at this stage it is useful for
16 xf86-video-freedreno and fdre (and eventual gallium driver) to be
22 driver and xf86-video-freedreno (ignoring the fbdev->KMS changes).
25 module or a DRM driver.. it is just an attempt to paper over a non-
/third_party/mesa3d/src/
Dmeson.build28 inc_virtio_gpu = include_directories('virtio/virtio-gpu')
55 command : [prog_python, git_sha1_gen_py, '--output', '@OUTPUT@'],
72 if with_tools.contains('drm-shim')
73 subdir('drm-shim') subdir
79 subdir('egl/wayland/wayland-drm')
/third_party/mesa3d/src/broadcom/
Dmeson.build34 if with_tools.contains('drm-shim')
35 subdir('drm-shim') subdir
41 'libbroadcom-v' + ver,
47 c_args : [no_override_init_args, '-DV3D_VERSION=' + ver],
53 v3d_args = ['-DV3D_BUILD_NEON']
57 v3d_neon_c_args = '-mfpu=neon'
/third_party/mesa3d/src/gallium/drivers/lima/
Dmeson.build95 '-p', join_paths(meson.source_root(), 'src/compiler/nir/'),
112 compile_args : '-DGALLIUM_LIMA',
160 if with_tools.contains('drm-shim')
161 subdir('drm-shim') subdir
/third_party/mesa3d/src/etnaviv/drm-shim/
Detnaviv_noop.c18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
30 #include "drm-uapi/etnaviv_drm.h"
31 #include "drm-shim/drm_shim.h"
168 drm_shim_bo_init(bo, create->size); in etnaviv_ioctl_gem_new()
169 create->handle = drm_shim_bo_get_handle(shim_fd, bo); in etnaviv_ioctl_gem_new()
180 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle); in etnaviv_ioctl_gem_info()
182 args->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo); in etnaviv_ioctl_gem_info()
193 if (gp->param > ETNAVIV_PARAM_SOFTPIN_START_ADDR) { in etnaviv_ioctl_get_param()
194 fprintf(stderr, "Unknown DRM_IOCTL_ETNAVIV_GET_PARAM %d\n", gp->param); in etnaviv_ioctl_get_param()
195 return -1; in etnaviv_ioctl_get_param()
[all …]
/third_party/mesa3d/src/gallium/drivers/lima/drm-shim/
Dlima_noop.c28 #include "drm-shim/drm_shim.h"
29 #include "drm-uapi/lima_drm.h"
46 switch (gp->param) { in lima_ioctl_get_param()
48 gp->value = DRM_LIMA_PARAM_GPU_ID_MALI450; in lima_ioctl_get_param()
51 gp->value = 6; in lima_ioctl_get_param()
54 fprintf(stderr, "Unknown DRM_IOCTL_LIMA_GET_PARAM %d\n", gp->param); in lima_ioctl_get_param()
55 return -1; in lima_ioctl_get_param()
66 size_t size = ALIGN(create->size, 4096); in lima_ioctl_gem_create()
70 create->handle = drm_shim_bo_get_handle(shim_fd, bo); in lima_ioctl_gem_create()
83 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, gem_info->handle); in lima_ioctl_gem_info()
[all …]
/third_party/mesa3d/src/freedreno/drm-shim/
Dfreedreno_noop.c27 #include "drm-shim/drm_shim.h"
28 #include "drm-uapi/msm_drm.h"
54 size_t size = ALIGN(create->size, 4096); in msm_ioctl_gem_new()
57 return -EINVAL; in msm_ioctl_gem_new()
68 create->handle = drm_shim_bo_get_handle(shim_fd, bo); in msm_ioctl_gem_new()
80 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle); in msm_ioctl_gem_info()
83 return -ENOENT; in msm_ioctl_gem_info()
85 switch (args->info) { in msm_ioctl_gem_info()
87 args->value = drm_shim_bo_get_mmap_offset(shim_fd, bo); in msm_ioctl_gem_info()
90 args->value = bo->mem_addr; in msm_ioctl_gem_info()
[all …]
/third_party/mesa3d/src/panfrost/drm-shim/
Dpanfrost_noop.c28 #include "drm-shim/drm_shim.h"
29 #include "drm-uapi/panfrost_drm.h"
33 /* Default GPU ID if PAN_GPU_ID is not set. This defaults to Mali-G52. */
49 switch (gp->param) { in pan_ioctl_get_param()
55 gp->value = strtol(override_version, NULL, 16); in pan_ioctl_get_param()
57 gp->value = PAN_GPU_ID_DEFAULT; in pan_ioctl_get_param()
64 gp->value = 0xF; in pan_ioctl_get_param()
67 gp->value = 0x809; in pan_ioctl_get_param()
72 gp->value = ~0; in pan_ioctl_get_param()
77 gp->value = 0; in pan_ioctl_get_param()
[all …]
/third_party/mesa3d/src/broadcom/drm-shim/
Dvc4_noop.c28 #include "drm-uapi/vc4_drm.h"
29 #include "drm-shim/drm_shim.h"
46 drm_shim_bo_init(bo, create->size); in vc4_ioctl_create_bo()
47 create->handle = drm_shim_bo_get_handle(shim_fd, bo); in vc4_ioctl_create_bo()
58 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, map->handle); in vc4_ioctl_mmap_bo()
60 map->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo); in vc4_ioctl_mmap_bo()
76 switch (gp->param) { in vc4_ioctl_get_param()
81 gp->value = 1; in vc4_ioctl_get_param()
86 gp->value = 0; in vc4_ioctl_get_param()
93 if (gp->param < ARRAY_SIZE(param_map) && param_map[gp->param]) { in vc4_ioctl_get_param()
[all …]
Dv3d_noop.c28 #include "drm-uapi/v3d_drm.h"
29 #include "drm-shim/drm_shim.h"
65 drm_shim_bo_init(&bo->base, create->size); in v3d_ioctl_create_bo()
67 assert(UINT_MAX - v3d.next_offset > create->size); in v3d_ioctl_create_bo()
68 bo->offset = v3d.next_offset; in v3d_ioctl_create_bo()
69 v3d.next_offset += create->size; in v3d_ioctl_create_bo()
71 create->offset = bo->offset; in v3d_ioctl_create_bo()
72 create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base); in v3d_ioctl_create_bo()
74 drm_shim_bo_put(&bo->base); in v3d_ioctl_create_bo()
84 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, args->handle); in v3d_ioctl_get_bo_offset()
[all …]
/third_party/libdrm/exynos/
Dexynos_drm.h6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
32 #include "drm.h"
35 * User-desired buffer creation information structure.
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
41 * - this handle will be set by gem module of kernel side.
82 /* Physically Non-Continuous memory. */
84 /* non-cachable mapping and used as default. */
88 /* write-combine mapping. */
/third_party/mesa3d/docs/relnotes/
D21.1.8.rst1 Mesa 21.1.8 Release Notes / 2021-09-08
18 ---------------
22 5cd32f5d089dca75300578a3d771a656eaed652090573a2655fe4e7022d56bfc mesa-21.1.8.tar.xz
26 ------------
28 - None
32 ---------
34 - llvmpipe doesn't compile a valid shader with an useless switch
35 - GetFragDataLocation(prog, "gl_FragColor") generates INVALID_OPERATION, but specs don't say it sho…
36 - Possible miscompilation of a comparison with unsigned zero
37 - dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info crash on Android R
[all …]
/third_party/mesa3d/src/intel/dev/
Dmeson.build53 if with_tests and with_tools.contains('drm-shim') and with_tools.contains('intel')
/third_party/mesa3d/src/intel/tools/
Dintel_noop_drm_shim.c37 #include "drm-uapi/i915_drm.h"
38 #include "drm-shim/drm_shim.h"
68 struct i915_bo *bo = (struct i915_bo *) drm_shim_bo_lookup(shim_fd, tiling_arg->handle); in i915_ioctl_gem_set_tiling()
71 return -1; in i915_ioctl_gem_set_tiling()
73 bo->tiling_mode = tiling_arg->tiling_mode; in i915_ioctl_gem_set_tiling()
74 bo->stride = tiling_arg->stride; in i915_ioctl_gem_set_tiling()
84 struct i915_bo *bo = (struct i915_bo *) drm_shim_bo_lookup(shim_fd, tiling_arg->handle); in i915_ioctl_gem_get_tiling()
87 return -1; in i915_ioctl_gem_get_tiling()
89 tiling_arg->tiling_mode = bo->tiling_mode; in i915_ioctl_gem_get_tiling()
90 tiling_arg->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; in i915_ioctl_gem_get_tiling()
[all …]

12