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Searched +full:exynos5250 +full:- +full:usbdrd +full:- +full:phy (Results 1 – 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dsamsung-phy.txt2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
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Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
50 #address-cells = <1>;
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/kernel/linux/linux-6.6/arch/arm/boot/dts/samsung/
Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
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Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
46 #address-cells = <1>;
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Dexynos5250-smdk5250.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/maxim,max77686.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "exynos5250.dtsi"
16 model = "Samsung SMDK5250 board based on Exynos5250";
17 compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
31 stdout-path = "serial2:115200n8";
34 vdd: fixed-regulator-vdd {
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Dexynos5250-arndale.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 based Arndale board device tree source
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
15 #include "exynos5250.dtsi"
18 model = "Insignal Arndale evaluation board based on Exynos5250";
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Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
14 #include "exynos5250.dtsi"
18 compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
19 chassis-type = "laptop";
33 stdout-path = "serial3:115200n8";
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Dexynos5250-snow-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
13 #include "exynos5250.dtsi"
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
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/kernel/linux/linux-5.10/drivers/phy/samsung/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
3 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
4 obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
5 obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o
6 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
7 phy-exynos-usb2-y += phy-samsung-usb2.o
8 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
9 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
10 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
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Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
20 #include <linux/phy/phy.h>
26 #include <linux/soc/samsung/exynos-regs-pmu.h>
28 /* Exynos USB PHY registers */
37 /* Exynos5: USB 3.0 DRD PHY registers */
130 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
176 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
178 * @reg_phy: usb phy controller register memory base
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/kernel/linux/linux-6.6/drivers/phy/samsung/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
3 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
4 obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
5 obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
6 phy-exynos-ufs-y += phy-samsung-ufs.o
7 phy-exynos-ufs-y += phy-exynos7-ufs.o
8 phy-exynos-ufs-y += phy-exynosautov9-ufs.o
9 phy-exynos-ufs-y += phy-fsd-ufs.o
10 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
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Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung Exynos5 SoC series USB DRD PHY driver
5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
18 #include <linux/phy/phy.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
26 /* Exynos USB PHY registers */
36 /* Exynos5: USB 3.0 DRD PHY registers */
129 /* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */
148 /* Exynos850: USB DRD PHY registers */
204 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
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