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Searched +full:fu540 +full:- +full:c000 +full:- +full:ccache (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/
Dsifive,ccache0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/
Dsifive-l2-cache.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
18 acts as directory-based coherency manager.
22 - $ref: /schemas/cache-controller.yaml#
29 - sifive,fu540-c000-ccache
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/kernel/linux/linux-6.6/arch/riscv/boot/dts/sifive/
Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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/kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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/kernel/linux/linux-6.6/drivers/soc/sifive/
Dsifive_ccache.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 SiFive, Inc.
9 #define pr_fmt(fmt) "CCACHE: " fmt
68 return -EINVAL; in ccache_write()
72 return -EINVAL; in ccache_write()
107 { .compatible = "sifive,fu540-c000-ccache" },
108 { .compatible = "sifive,fu740-c000-ccache" },
154 if (this_leaf->level == level) in ccache_get_priv_group()
182 panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); in ccache_int_handler()
216 return -ENODEV; in sifive_ccache_init()
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/kernel/linux/linux-6.6/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
[all …]
/kernel/linux/linux-5.10/drivers/soc/sifive/
Dsifive_l2_cache.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 SiFive, Inc.
53 return -EINVAL; in l2_write()
57 return -EINVAL; in l2_write()
95 { .compatible = "sifive,fu540-c000-ccache" },
139 if (this_leaf->level == 2) in l2_get_priv_group()
188 return -ENODEV; in sifive_l2_init()
191 return -ENODEV; in sifive_l2_init()
195 return -ENOMEM; in sifive_l2_init()