Home
last modified time | relevance | path

Searched +full:gce +full:- +full:mailbox (Results 1 – 17 of 17) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt1 MediaTek GCE
4 The Global Command Engine (GCE) is used to help read/write registers with
6 vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
8 CMDQ driver uses mailbox framework for communication. Please refer to
9 mailbox.txt for generic information about mailbox device-tree bindings.
12 - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
13 "mediatek,mt6779-gce".
14 - reg: Address range of the GCE unit
15 - interrupts: The interrupt signal from the GCE block
16 - clock: Clocks according to the common clock binding
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mailbox/
Dmediatek,gce-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Global Command Engine Mailbox
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is used to help read/write registers with
15 vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
20 - enum:
21 - mediatek,mt6779-gce
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mmsys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
18 pattern: "^syscon@[0-9a-f]+$"
22 - items:
23 - enum:
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
[all …]
/kernel/linux/linux-5.10/include/linux/soc/mediatek/
Dmtk-cmdq.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/mailbox/mtk-cmdq-mailbox.h>
36 * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
38 * @dev: device of CMDQ mailbox client
51 * cmdq_mbox_create() - create CMDQ mailbox client and channel
52 * @dev: device of CMDQ mailbox client
53 * @index: index of CMDQ mailbox channel
54 * @timeout: timeout of a pkt execution by GCE, in unit of microsecond, set
57 * Return: CMDQ mailbox client pointer
63 * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
[all …]
/kernel/linux/linux-6.6/include/linux/soc/mediatek/
Dmtk-cmdq.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/mailbox/mtk-cmdq-mailbox.h>
33 * cmdq_dev_get_client_reg() - parse cmdq client reg from the device
35 * @dev: device of CMDQ mailbox client
48 * cmdq_mbox_create() - create CMDQ mailbox client and channel
49 * @dev: device of CMDQ mailbox client
50 * @index: index of CMDQ mailbox channel
52 * Return: CMDQ mailbox client pointer
57 * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
58 * @client: the CMDQ mailbox client
[all …]
/kernel/linux/linux-5.10/drivers/mailbox/
Dmtk-cmdq-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
8 #include <linux/dma-mapping.h>
17 #include <linux/mailbox/mtk-cmdq-mailbox.h>
21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
66 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
88 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa()
90 return cmdq->shift_pa; in cmdq_get_shift_pa()
98 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); in cmdq_thread_suspend()
101 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) in cmdq_thread_suspend()
[all …]
/kernel/linux/linux-6.6/drivers/mailbox/
Dmtk-cmdq-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
8 #include <linux/dma-mapping.h>
17 #include <linux/mailbox/mtk-cmdq-mailbox.h>
21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE)
71 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
95 WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); in cmdq_sw_ddr_enable()
98 writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable()
100 writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); in cmdq_sw_ddr_enable()
102 clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); in cmdq_sw_ddr_enable()
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
[all …]
Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
10 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
11 #include <dt-bindings/memory/mt6795-larb-port.h>
12 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
13 #include <dt-bindings/power/mt6795-power.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
18 interrupt-parent = <&sysirq>;
[all …]
Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
[all …]
Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
[all …]
Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
[all …]
Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include <dt-bindings/phy/phy.h>
13 #include "mt8183-pinfunc.h"
17 interrupt-parent = <&sysirq>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/
Dmtk_drm_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/soc/mediatek/mtk-cmdq.h>
9 #include <linux/soc/mediatek/mtk-mmsys.h>
27 * struct mtk_drm_crtc - MediaTek specific crtc structure.
84 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_drm_crtc_finish_page_flip()
87 spin_lock_irqsave(&crtc->dev->event_lock, flags); in mtk_drm_crtc_finish_page_flip()
88 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); in mtk_drm_crtc_finish_page_flip()
90 mtk_crtc->event = NULL; in mtk_drm_crtc_finish_page_flip()
91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in mtk_drm_crtc_finish_page_flip()
96 drm_crtc_handle_vblank(&mtk_crtc->base); in mtk_drm_finish_page_flip()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/
Dmtk_drm_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
29 * struct mtk_drm_crtc - MediaTek specific crtc structure.
93 struct drm_crtc *crtc = &mtk_crtc->base; in mtk_drm_crtc_finish_page_flip()
96 spin_lock_irqsave(&crtc->dev->event_lock, flags); in mtk_drm_crtc_finish_page_flip()
97 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); in mtk_drm_crtc_finish_page_flip()
99 mtk_crtc->event = NULL; in mtk_drm_crtc_finish_page_flip()
[all …]