| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v2_1.c | 144 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
146 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
149 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v2_1_init_gart_aperture_regs()
151 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v2_1_init_gart_aperture_regs()
160 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v2_1_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v2_1_init_system_aperture_regs()
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
167 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v2_1_init_system_aperture_regs()
236 if (adev->gmc.translate_further) { in gfxhub_v2_1_init_cache_regs()
323 !adev->gmc.noretry); in gfxhub_v2_1_setup_vmid_config()
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| D | amdgpu_gmc.c | 52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
85 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
89 amdgpu_bo_unref(&adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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| D | gmc_v9_0.c | 734 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
735 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
738 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_set_irq_funcs()
739 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
740 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
824 if (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb()
859 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
927 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
969 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb_pasid()
1160 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
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| D | gmc_v8_0.c | 35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
259 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v8_0_init_microcode()
262 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode()
291 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
294 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
297 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
300 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
303 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
360 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
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| D | gfxhub_v1_0.c | 58 if (adev->gmc.pdb0_bo) in gfxhub_v1_0_init_gart_aperture_regs()
59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_0_init_gart_aperture_regs()
68 if (adev->gmc.pdb0_bo) { in gfxhub_v1_0_init_gart_aperture_regs()
70 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
72 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
77 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
80 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
82 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
85 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
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| D | gmc_v7_0.c | 40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
158 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v7_0_init_microcode()
161 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode()
182 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
185 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
188 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
191 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
194 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
285 adev->gmc.vram_start >> 12); in gmc_v7_0_mc_program()
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| D | gmc_v10_0.c | 190 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
191 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
194 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
195 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
248 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
306 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
597 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
677 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
678 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
742 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v10_0_early_init()
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| D | gmc_v11_0.c | 155 adev->gmc.vm_fault.num_types = 1; in gmc_v11_0_set_irq_funcs()
156 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; in gmc_v11_0_set_irq_funcs()
159 adev->gmc.ecc_irq.num_types = 1; in gmc_v11_0_set_irq_funcs()
160 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; in gmc_v11_0_set_irq_funcs()
209 spin_lock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_vm_hub()
267 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v11_0_flush_vm_hub()
502 adev->gmc.vram_start; in gmc_v11_0_get_vm_pde()
505 if (!adev->gmc.translate_further) in gmc_v11_0_get_vm_pde()
585 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; in gmc_v11_0_set_gmc_funcs()
648 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v11_0_early_init()
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| D | gfxhub_v1_2.c | 80 if (adev->gmc.pdb0_bo) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
81 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
91 if (adev->gmc.pdb0_bo) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
94 (u32)(adev->gmc.fb_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
101 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
108 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
111 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
115 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
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| D | amdgpu_xgmi.c | 324 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
485 if (!adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
496 if (hive->hive_id == adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
548 hive->hive_id = adev->gmc.xgmi.hive_id; in amdgpu_get_xgmi_hive()
619 request_adev->gmc.xgmi.node_id, in amdgpu_xgmi_set_pstate()
620 request_adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_set_pstate()
651 adev->gmc.xgmi.node_id, in amdgpu_xgmi_update_topology()
652 adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_update_topology()
672 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) in amdgpu_xgmi_get_hops_count()
684 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) in amdgpu_xgmi_get_num_links()
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| D | gmc_v6_0.c | 38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
135 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name); in gmc_v6_0_init_microcode()
140 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v6_0_init_microcode()
153 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
250 adev->gmc.vram_start >> 12); in gmc_v6_0_mc_program()
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| D | gfxhub_v1_1.c | 88 if (max_region || adev->gmc.xgmi.connected_to_cpu) { in gfxhub_v1_1_get_xgmi_info()
89 adev->gmc.xgmi.num_physical_nodes = max_region + 1; in gfxhub_v1_1_get_xgmi_info()
91 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) in gfxhub_v1_1_get_xgmi_info()
95 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
99 adev->gmc.xgmi.physical_node_id = in gfxhub_v1_1_get_xgmi_info()
104 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) in gfxhub_v1_1_get_xgmi_info()
107 adev->gmc.xgmi.node_segment_size = seg_size; in gfxhub_v1_1_get_xgmi_info()
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| D | mmhub_v1_8.c | 48 adev->gmc.fb_start = base; in mmhub_v1_8_get_fb_location()
49 adev->gmc.fb_end = top; in mmhub_v1_8_get_fb_location()
82 if (adev->gmc.pdb0_bo) in mmhub_v1_8_init_gart_aperture_regs()
83 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_8_init_gart_aperture_regs()
94 if (adev->gmc.pdb0_bo) { in mmhub_v1_8_init_gart_aperture_regs()
97 (u32)(adev->gmc.fb_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
100 (u32)(adev->gmc.fb_start >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
104 (u32)(adev->gmc.gart_end >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
107 (u32)(adev->gmc.gart_end >> 44)); in mmhub_v1_8_init_gart_aperture_regs()
112 (u32)(adev->gmc.gart_start >> 12)); in mmhub_v1_8_init_gart_aperture_regs()
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| D | amdgpu_gmc.h | 77 * GMC page fault information
338 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((ad…
340 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
342 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((…
343 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(…
344 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
345 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (l…
346 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapp…
348 (adev)->gmc.gmc_funcs->override_vm_pte_flags \
350 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
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| D | aqua_vanjaram.c | 409 if (adev->gmc.num_mem_partitions == 1) in __aqua_vanjaram_get_auto_mode()
412 if (adev->gmc.num_mem_partitions == num_xcc) in __aqua_vanjaram_get_auto_mode()
415 if (adev->gmc.num_mem_partitions == num_xcc / 2) in __aqua_vanjaram_get_auto_mode()
419 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) in __aqua_vanjaram_get_auto_mode()
434 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; in __aqua_vanjaram_is_valid_mode()
436 return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0; in __aqua_vanjaram_is_valid_mode()
438 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
439 adev->gmc.num_mem_partitions == 3) && in __aqua_vanjaram_is_valid_mode()
443 return (adev->gmc.num_mem_partitions == 1 || in __aqua_vanjaram_is_valid_mode()
444 adev->gmc.num_mem_partitions == 4) && in __aqua_vanjaram_is_valid_mode()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_xgmi.c | 220 return snprintf(buf, PAGE_SIZE, "%llu\n", adev->gmc.xgmi.node_id); in amdgpu_xgmi_show_device_id()
330 if (!adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
342 if (hive->hive_id == adev->gmc.xgmi.hive_id) in amdgpu_get_xgmi_hive()
367 hive->hive_id = adev->gmc.xgmi.hive_id; in amdgpu_get_xgmi_hive()
433 request_adev->gmc.xgmi.node_id, in amdgpu_xgmi_set_pstate()
434 request_adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_set_pstate()
462 adev->gmc.xgmi.node_id, in amdgpu_xgmi_update_topology()
463 adev->gmc.xgmi.hive_id, ret); in amdgpu_xgmi_update_topology()
483 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) in amdgpu_xgmi_get_hops_count()
497 if (!adev->gmc.xgmi.supported) in amdgpu_xgmi_add_device()
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| D | gmc_v7_0.c | 40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v7_0_init_microcode()
162 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v7_0_init_microcode()
167 release_firmware(adev->gmc.fw); in gmc_v7_0_init_microcode()
168 adev->gmc.fw = NULL; in gmc_v7_0_init_microcode()
189 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode()
192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode()
195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v7_0_mc_load_microcode()
198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v7_0_mc_load_microcode()
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| D | gmc_v10_0.c | 150 adev->gmc.vm_fault.num_types = 1; in gmc_v10_0_set_irq_funcs()
151 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; in gmc_v10_0_set_irq_funcs()
154 adev->gmc.ecc_irq.num_types = 1; in gmc_v10_0_set_irq_funcs()
155 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; in gmc_v10_0_set_irq_funcs()
205 spin_lock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
257 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v10_0_flush_vm_hub()
539 adev->gmc.vram_start; in gmc_v10_0_get_vm_pde()
542 if (!adev->gmc.translate_further) in gmc_v10_0_get_vm_pde()
612 if (adev->gmc.gmc_funcs == NULL) in gmc_v10_0_set_gmc_funcs()
613 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; in gmc_v10_0_set_gmc_funcs()
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| D | gmc_v8_0.c | 35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
276 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v8_0_init_microcode()
279 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v8_0_init_microcode()
284 release_firmware(adev->gmc.fw); in gmc_v8_0_init_microcode()
285 adev->gmc.fw = NULL; in gmc_v8_0_init_microcode()
314 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
317 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
320 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
323 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
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| D | gmc_v6_0.c | 38 #include "gmc/gmc_6_0_d.h"
39 #include "gmc/gmc_6_0_sh_mask.h"
134 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
138 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v6_0_init_microcode()
145 release_firmware(adev->gmc.fw); in gmc_v6_0_init_microcode()
146 adev->gmc.fw = NULL; in gmc_v6_0_init_microcode()
159 if (!adev->gmc.fw) in gmc_v6_0_mc_load_microcode()
162 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v6_0_mc_load_microcode()
166 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v6_0_mc_load_microcode()
169 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v6_0_mc_load_microcode()
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| D | amdgpu_gmc.c | 131 if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) in amdgpu_gmc_agp_addr()
134 return adev->gmc.agp_start + ttm->dma_address[0]; in amdgpu_gmc_agp_addr()
182 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); in amdgpu_gmc_gart_location()
272 struct amdgpu_gmc *gmc = &adev->gmc; in amdgpu_gmc_filter_faults() local
281 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) in amdgpu_gmc_filter_faults()
286 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; in amdgpu_gmc_filter_faults()
294 fault = &gmc->fault_ring[fault->next]; in amdgpu_gmc_filter_faults()
302 fault = &gmc->fault_ring[gmc->last_fault]; in amdgpu_gmc_filter_faults()
307 fault->next = gmc->fault_hash[hash].idx; in amdgpu_gmc_filter_faults()
308 gmc->fault_hash[hash].idx = gmc->last_fault++; in amdgpu_gmc_filter_faults()
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| D | gmc_v9_0.c | 645 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
646 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
649 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
650 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
729 if (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb()
759 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
817 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
856 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb_pasid()
1038 adev->gmc.vram_start; in gmc_v9_0_get_vm_pde()
1041 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
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| D | gfxhub_v1_0.c | 59 (u32)(adev->gmc.gart_start >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
61 (u32)(adev->gmc.gart_start >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
64 (u32)(adev->gmc.gart_end >> 12)); in gfxhub_v1_0_init_gart_aperture_regs()
66 (u32)(adev->gmc.gart_end >> 44)); in gfxhub_v1_0_init_gart_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
81 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); in gfxhub_v1_0_init_system_aperture_regs()
93 max((adev->gmc.fb_end >> 18) + 0x1, in gfxhub_v1_0_init_system_aperture_regs()
94 adev->gmc.agp_end >> 18)); in gfxhub_v1_0_init_system_aperture_regs()
98 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); in gfxhub_v1_0_init_system_aperture_regs()
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| D | amdgpu_gmc.h | 66 * GMC page fault information
245 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((ad…
247 ((adev)->gmc.gmc_funcs->flush_gpu_tlb_pasid \
249 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((…
250 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping(…
251 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags))
252 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (l…
253 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapp…
254 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))
264 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) in amdgpu_gmc_vram_full_visible() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/loongson/ |
| D | lsdc_gfxpll.c | 15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
23 * ---+---> | div_ref | ---> | loopc | --+--> | / div_out_1 | _____/ _____ GMC
36 unsigned div_out_gmc : 7; /* 13 : 7 GMC output clock divider */
45 unsigned sel_out_gmc : 1; /* 41 gmc output clk enable */
82 unsigned int *gmc, in loongson_gfxpll_get_rates() argument
110 if (gmc) in loongson_gfxpll_get_rates()
111 *gmc = gmc_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
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