| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8qm-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
[all …]
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| D | imx8-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
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| D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
[all …]
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| D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 lsio_mem_clk: clock-lsio-mem {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
[all …]
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| D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
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| D | imx8dxl-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
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| D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8-clock.h>
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
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| D | imx8qxp-ai_ml.dts | 1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include "imx8qxp.dtsi"
13 compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
22 stdout-path = &lpuart2;
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_leds>;
35 user-led1 {
38 linux,default-trigger = "heartbeat";
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
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| D | imx8qxp-ai_ml.dts | 1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
9 #include "imx8qxp.dtsi"
13 compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
22 stdout-path = &adma_lpuart2;
31 compatible = "gpio-leds";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_leds>;
35 user-led1 {
38 linux,default-trigger = "heartbeat";
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,scu.txt | 2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/ |
| D | nxp,imx8qxp-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP IMX8QXP ADC
10 - Cai Huoqing <caihuoqing@baidu.com>
13 Supports the ADC found on the IMX8QXP SoC.
17 const: nxp,imx8qxp-adc
28 clock-names:
30 - const: per
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/ |
| D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | fsl,scu-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol
10 - Abel Vesa <abel.vesa@nxp.com>
13 Client nodes are maintained as children of the relevant IMX-SCU device node.
15 (Documentation/devicetree/bindings/clock/clock-bindings.txt)
18 include/dt-bindings/clock/imx8qxp-clock.h
23 - enum:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/ |
| D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
[all …]
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| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
| D | 0001_linux_arch.patch | 7 Change-Id: I8c7b42f8858212fb4b2d56a871d3f4d5afc73954
9 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
11 --- a/arch/arm64/Kconfig
13 @@ -183,7 +183,6 @@ config ARM64
17 - select HOLES_IN_ZONE
21 @@ -1023,6 +1022,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
31 @@ -1148,7 +1150,7 @@ config XEN
35 - int
40 @@ -1182,15 +1184,6 @@ config UNMAP_KERNEL_AT_EL0
44 -config MITIGATE_SPECTRE_BRANCH_HISTORY
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
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| D | clk-imx8qxp-lpcg.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
44 * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
166 unsigned int idx = clkspec->args[0] / 4; in imx_lpcg_of_clk_src_get()
168 if (idx >= hw_data->num) { in imx_lpcg_of_clk_src_get()
170 return ERR_PTR(-EINVAL); in imx_lpcg_of_clk_src_get()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/bus/ |
| D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-cpu.o
8 mxc-clk-objs += clk-divider-gate.o
9 mxc-clk-objs += clk-fixup-div.o
10 mxc-clk-objs += clk-fixup-mux.o
11 mxc-clk-objs += clk-frac-pll.o
[all …]
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| D | clk-imx8qxp-lpcg.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
44 * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
162 struct device *dev = &pdev->dev; in imx8qxp_lpcg_clk_probe()
163 struct device_node *np = dev->of_node; in imx8qxp_lpcg_clk_probe()
174 return -ENODEV; in imx8qxp_lpcg_clk_probe()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/ |
| D | fsl,asrc.txt | 11 - compatible : Compatible list, should contain one of the following
13 "fsl,imx35-asrc",
14 "fsl,imx53-asrc",
15 "fsl,imx8qm-asrc",
16 "fsl,imx8qxp-asrc",
18 - reg : Offset and length of the register set for the device.
20 - interrupts : Contains the spdif interrupt.
22 - dmas : Generic dma devicetree binding as described in
25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
27 - clocks : Contains an entry for each entry in clock-names.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | fsl,asrc.txt | 11 - compatible : Compatible list, should contain one of the following
13 "fsl,imx35-asrc",
14 "fsl,imx53-asrc",
15 "fsl,imx8qm-asrc",
16 "fsl,imx8qxp-asrc",
18 - reg : Offset and length of the register set for the device.
20 - interrupts : Contains the spdif interrupt.
22 - dmas : Generic dma devicetree binding as described in
25 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
27 - clocks : Contains an entry for each entry in clock-names.
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
47 "#size-cells":
52 - description: pixel clock
[all …]
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