| /arkcompiler/runtime_core/static_core/compiler/optimizer/ir_builder/ |
| D | inst_templates.yaml | 1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
28 if (graph_->IsBytecodeOptimizer()) {
[all …]
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| /arkcompiler/runtime_core/compiler/optimizer/ir/ |
| D | instructions.yaml | 1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 Opcode of the instruction
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
26 …C++ base that represent this opcode. In far future if we managed to generate also instruction clas…
30 Properties of the instruction, such as: arithmetic, binop, throw, etc
33 Modes which the instruction can be used in
36 # Templates aim to reduce boilerplate in instruction description.
39 - equal_common_types
40 - float_src_eq_dst_size
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| /arkcompiler/runtime_core/static_core/libllvmbackend/transforms/passes/ |
| D | gep_propagation.h | 2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 class Instruction; variable
39 // NOLINTNEXTLINE(readability-identifier-naming)
43 …sing SelectorSplitMap = llvm::DenseMap<llvm::Instruction *, std::pair<llvm::Instruction *, llvm::I…
45 void AddToVector(llvm::Instruction *inst, llvm::SmallVector<llvm::Instruction *> *toExpand,
46 llvm::SmallVector<llvm::Instruction *> *selectors);
50 …void SplitGepSelectors(llvm::Function *function, llvm::SmallVector<llvm::Instruction *> *selectors,
51 llvm::DenseMap<llvm::Instruction *, llvm::Instruction *> *sgeps);
53 … std::pair<llvm::Value *, llvm::Value *> GenerateInput(llvm::Value *input, llvm::Instruction *inst,
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| D | gep_propagation.cpp | 2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
27 #define DEBUG_TYPE "gep-propagation"
41 using llvm::Instruction;
47 /// Optimize no-op PHINodes and Selects in place.
48 // NOLINTNEXTLINE(fuchsia-statically-constructed-objects)
49 static llvm::cl::opt<bool> g_optimizeNoop("gprop-optimize", llvm::cl::Hidden, llvm::cl::init(true));
64 void GepPropagation::AddToVector(Instruction *inst, SmallVector<Instruction *> *toExpand, in AddToVector()
65 SmallVector<Instruction *> *selectors) in AddToVector()
67 switch (inst->getOpcode()) { in AddToVector()
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| D | aarch64_fixup_sdiv.cpp | 7 * http://www.apache.org/licenses/LICENSE-2.0
22 #define DEBUG_TYPE "aarch64-fixup-sdiv"
32 bool AArch64FixupSDiv::ReplaceSelect(llvm::Instruction *selectInst) in ReplaceSelect()
34 auto cmp = llvm::cast<llvm::Instruction>(selectInst->getOperand(0U)); in ReplaceSelect()
35 auto sub = selectInst->getOperand(1U); in ReplaceSelect()
36 auto sdiv = selectInst->getOperand(2U); in ReplaceSelect()
38 // sub instruction may be replaced with value in ReplaceSelect()
39 auto sdivInst = llvm::cast<llvm::Instruction>(sdiv); in ReplaceSelect()
41 selectInst->replaceAllUsesWith(sdivInst); in ReplaceSelect()
42 sdivInst->takeName(selectInst); in ReplaceSelect()
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| D | intrinsics_lowering.cpp | 2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
52 std::unordered_map<llvm::Instruction *, llvm::Instruction *> instToReplaceWithInst; in run()
54 for (auto &instruction : block) { in run() local
55 auto llvmIntrinsicId = arkInterface_->GetLLVMIntrinsicId(&instruction); in run()
57 ASSERT(llvm::isa<llvm::CallInst>(&instruction)); in run()
58 … changed |= ReplaceWithLLVMIntrinsic(llvm::cast<llvm::CallInst>(&instruction), llvmIntrinsicId); in run()
61 auto intrinsicId = arkInterface_->GetIntrinsicId(&instruction); in run()
66 auto opcode = instruction.getOpcode(); in run()
67 if (opcode == llvm::Instruction::Call) { in run()
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| D | intrinsics_lowering.h | 2 * Copyright (c) 2023-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
32 class Instruction; variable
49 // NOLINTNEXTLINE(readability-identifier-naming)
56 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
58 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
60 bool HandleFRem(llvm::Instruction *inst, LLVMArkInterface::IntrinsicId intrinsicId,
61 … std::unordered_map<llvm::Instruction *, llvm::Instruction *> *instToReplaceWithInst);
67 static constexpr llvm::StringRef ARG_NAME = "intrinsics-lowering";
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| /arkcompiler/runtime_core/compiler/optimizer/ir_builder/ |
| D | inst_templates.yaml | 1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
28 if (graph_->IsBytecodeOptimizer()) {
[all …]
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| /arkcompiler/ets_frontend/testTs/instype/ |
| D | recordthis-expected.txt | 2 (instruction order, type): (-2, 111), (-1, 106),
4 (instruction order, type): (-2, 111), (-1, 102),
6 (instruction order, type): (-2, 111), (-1, 103),
8 (instruction order, type): (-2, 111), (-1, 104),
10 (instruction order, type): (-2, 111), (-1, 105),
12 (instruction order, type): (-2, 111), (-1, 107), (16, 4),
14 (instruction order, type): (-2, 101), (-1, 108),
16 (instruction order, type): (-2, 111), (-1, 109),
18 (instruction order, type): (-2, 111), (-1, 110),
20 (instruction order, type): (-1, 112), (9, 1),
[all …]
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| D | recordimport-expected.txt | 2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
12 (instruction order, type): (5, 101), (8, 105), (19, 107), (22, 102), (25, 103), (31, 104), (37, 106…
|
| D | recordexport-expected.txt | 2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
|
| /arkcompiler/runtime_core/docs/ |
| D | ir_format.md | 7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
60 * Supporting side exits for de-optimizations and removing cold code.
65 ## Instruction set
76 …ble to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those…
80 IR contains high- and low-level instructions with a single interface.
81 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
87 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
90 In Ahead-Of-Time(AOT) mode the overhead is less critical for us, so we can do more optimizations.
91 In Just-In-Time(JIT) mode need to strictly control the overhead to get the overall performance incr…
104 …e Assignment) form(used in LLVM, WebKit, HHVM, CoreCLR, IonMonkey) and Sea-of-Nodes(Hotspot, V8 Tu…
[all …]
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| /arkcompiler/runtime_core/compiler/docs/ |
| D | ir_builder.md | 18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
20 - constant hasn't type as well and if one constant is used in integer and float operations, it must…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
56 - set inputs from the virtual register map
57 - if has destination, update virtual register definition in the vreg map
58 6. If instruction is a terminator, goto 1, else goto 4.
[all …]
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| D | vn_doc.md | 5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
34 for (auto bb : GetGraph()->GetBlocksRPO()) {
35 for (auto inst : bb->AllInsts()) {
43 if (inst->IsNotCseApplicable()) {
[all …]
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| /arkcompiler/runtime_core/static_core/compiler/docs/ |
| D | ir_builder.md | 18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
20 - constant hasn't type as well and if one constant is used in integer and float operations, it must…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
56 - set inputs from the virtual register map
57 - if has destination, update virtual register definition in the vreg map
58 6. If instruction is a terminator, goto 1, else goto 4.
[all …]
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| D | memory_barriers_doc.md | 19 There is instruction flag `MEM_BARRIER`. The flag is set to `true` for the instructions NewObject, …
20 The pass `OptimizeMemoryBarriers` try remove the flag(set false) from the instruction.
21 …s through all instructions in PRO order. If the instruction has flag `MEM_BARRIER` we add the inst…
22 If we visit an instruction that can pass an object to another thread(Store instruction, Call instru…
23 If the instruction has input from the `barriers_insts_`, we call function `MergeBarriers`.
24 The function set `false` for the flag `MEM_BARRIER`, exclude last instruction from the vector.
25 So we will only set the barrier in the last instruction before potentially passing the created obje…
37 for (auto bb : GetGraph()->GetBlocksRPO()) {
38 for (auto inst : bb->Insts()) {
39 if (inst->GetFlag(inst_flags::MEM_BARRIER)) {
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| D | bridges.md | 8 2. Fix `SaveStates` for `source` instruction **ONLY** on path from `source` instructions to `target…
11 …is triggered between incorrect SaveState and usage then we will lost object - we will not find out…
14 We need to be sure that the `source` instruction dominates the `target` instruction.
17 …et` instruction to the `source` and we are looking for SS that need to be fixed. We always can do …
22 …tates` and, if it is required, `CreateBridgeInSS`. It inserts `source` instruction into `SaveState…
24 …eState inputs if it is not there. Delete object from the SaveState, if instruction does not domina…
26 …ng for search SaveState on path to `target`, which don't have `source` instruction in input. Retur…
30 …mpBridges`** write in your `std::ostream` all bridges which need add for this `source` instruction.
36 … be deleted or moved, but the pointer will not change. As a result, in instruction v10 we can use …
69 2. SaveState -> ... |
[all …]
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| D | vn_doc.md | 5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
34 for (auto bb : GetGraph()->GetBlocksRPO()) {
35 for (auto inst : bb->AllInsts()) {
43 if (inst->IsNotCseApplicable()) {
[all …]
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| /arkcompiler/runtime_core/tests/cts-generator/cts-template/ |
| D | jnez.obj.yaml | 1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jnez.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
26 instruction address.
28 - x_none
30 - sig: jnez.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
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| D | jeqz.obj.yaml | 1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jeqz.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
26 instruction address.
28 - x_none
30 - sig: jeqz.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
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| /arkcompiler/runtime_core/static_core/tests/cts-generator/cts-template/ |
| D | jnez.obj.yaml | 1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "jnez.obj"
20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
22 instruction address.
24 - x_none
26 - sig: jnez.obj imm:i32
30 - file-name: "invalid_offset"
33 - branch_target
35 - sig: jnez.obj imm:i32
[all …]
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| D | jeqz.obj.yaml | 1 # Copyright (c) 2021-2024 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 - file-name: "jeqz.obj"
20 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction…
22 instruction address.
24 - x_none
26 - sig: jeqz.obj imm:i32
30 - file-name: "invalid_offset"
33 - branch_target
35 - sig: jeqz.obj imm:i32
[all …]
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| /arkcompiler/runtime_core/static_core/docs/ |
| D | ir_format.md | 7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
69 * Supporting side exits for de-optimizations and removing cold code.
74 ## Instruction set
85 …ble to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those…
89 IR contains high- and low-level instructions with a single interface.
90 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
96 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
99 In Ahead-Of-Time(AOT) mode the overhead is less critical for us, so we can do more optimizations.
100 In Just-In-Time(JIT) mode need to strictly control the overhead to get the overall performance incr…
113 …e Assignment) form(used in LLVM, WebKit, HHVM, CoreCLR, IonMonkey) and Sea-of-Nodes(Hotspot, V8 Tu…
[all …]
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| /arkcompiler/runtime_core/bytecode_optimizer/ |
| D | bytecode_optimizer_isapi.rb | 1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 Instruction.class_eval do
48 @instruction_hash = Hash.new { |_, key| raise "No instruction with '#{key}' mnemonic" }
63 LOG(ERROR, BYTECODE_OPTIMIZER) << \"Codegen for \" << compiler::GetOpcodeString(inst->GetOpcode()) …
64 enc->success_ = false;
75 LOG(ERROR, BYTECODE_OPTIMIZER) << \"CheckWidth for \" << compiler::GetOpcodeString(inst->GetOpcode(…
76 re->success_ = false;
100 Leaf = Struct.new(:instruction, :args) do
104 if instruction.acc_read?
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/optimizations/ |
| D | lse.h | 2 * Copyright (c) 2021-2024 Huawei Device Co., Ltd.
7 * http://www.apache.org/licenses/LICENSE-2.0
33 * "Memory Instruction" -> "Value stored at location pointed by instruction"
43 * - if the instruction is a store and a stored value is equal to value from
45 * - if the instruction is a store and a value from heap for this store is
49 * instruction are invalidated.
50 * - if the instruction is a load and there is a value from the heap for this
52 * - if the instruction is a load and there is no value from the heap for this
55 * - if the instruction is a volatile load then the whole heap is invalidated.
56 * - if the instruction is a call then the whole heap is invalidated.
[all …]
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