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Searched +full:jh7110 +full:- +full:syscrg (Results 1 – 15 of 15) sorted by relevance

/kernel/linux/linux-6.6/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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Djh7110-starfive-visionfive-2-v1.2a.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
16 phy-mode = "rmii";
17 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
18 <&syscrg JH7110_SYSCLK_GMAC1_RX>;
19 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
20 <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
24 rx-internal-delay-ps = <1900>;
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Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dstarfive,jh7110-stgcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
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Dstarfive,jh7110-voutcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-voutcrg
21 - description: Vout Top core
22 - description: Vout Top Ahb
23 - description: Vout Top Axi
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Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
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Dstarfive,jh7110-aoncrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-aoncrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
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Dstarfive,jh7110-syscrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System Clock and Reset Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7110-syscrg
21 - items:
22 - description: Main Oscillator (24 MHz)
23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dstarfive,jh7110-tdm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-tdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 TDM Controller
11 integrated in StarFive JH7110 SoC, allowing up to 8 channels of
16 - Walker Chen <walker.chen@starfivetech.com>
19 - $ref: dai-common.yaml#
24 - starfive,jh7110-tdm
31 - description: TDM AHB Clock
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mmc/
Dstarfive,jh7110-mmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: synopsys-dw-mshc-common.yaml#
17 - William Qiu <william.qiu@starfivetech.com>
21 const: starfive,jh7110-mmc
28 - description: biu clock
29 - description: ciu clock
31 clock-names:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7110-sys-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 SYS Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
41 '#interrupt-cells':
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 USB 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb-phy
19 "#phy-cells":
24 - description: PHY 125m
25 - description: app 125m
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dstarfive,jh7110-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
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/kernel/linux/linux-6.6/drivers/clk/starfive/
Dclk-starfive-jh7110.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "clk-starfive-jh71x0.h"
7 /* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
Dclk-starfive-jh7110-sys.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 System Clock Driver
11 #include <linux/clk-provider.h>
17 #include <soc/starfive/reset-starfive-jh71x0.h>
19 #include <dt-bindings/clock/starfive,jh7110-crg.h>
21 #include "clk-starfive-jh7110.h"
329 unsigned int idx = clkspec->args[0]; in jh7110_sysclk_get()
332 return &priv->reg[idx].hw; in jh7110_sysclk_get()
334 return ERR_PTR(-EINVAL); in jh7110_sysclk_get()
363 return -ENOMEM; in jh7110_reset_controller_register()
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