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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pwm/
Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jitao Shi <jitao.shi@mediatek.com>
11 - Xinlei Lee <xinlei.lee@mediatek.com>
14 - $ref: pwm.yaml#
19 - enum:
20 - mediatek,mt2701-disp-pwm
21 - mediatek,mt6595-disp-pwm
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pwm/
Dpwm-mtk-disp.txt1 MediaTek display PWM controller
4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
8 - reg: physical base address and length of the controller's registers.
9 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - clock-names: must contain the following:
13 - "main": clock used to generate PWM signals.
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/kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mt8173-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/memory/mt8173-larb-port.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/mt8173-power.h>
13 #include <dt-bindings/reset/mt8173-resets.h>
14 #include <dt-bindings/gce/mt8173-gce.h>
15 #include <dt-bindings/thermal/thermal.h>
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Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
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/kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/
Dmtk_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/soc/mediatek/mtk-mmsys.h>
14 #include <linux/dma-mapping.h>
51 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
52 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
168 struct mtk_drm_private *private = drm->dev_private; in mtk_drm_kms_init()
175 return -EPROBE_DEFER; in mtk_drm_kms_init()
177 pdev = of_find_device_by_node(private->mutex_node); in mtk_drm_kms_init()
179 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", in mtk_drm_kms_init()
180 private->mutex_node); in mtk_drm_kms_init()
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/kernel/linux/linux-6.6/drivers/gpu/drm/mediatek/
Dmtk_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/dma-mapping.h>
50 if (info->num_planes != 1) in mtk_drm_mode_fb_create()
51 return ERR_PTR(-EINVAL); in mtk_drm_mode_fb_create()
316 { .compatible = "mediatek,mt2701-mmsys",
318 { .compatible = "mediatek,mt7623-mmsys",
320 { .compatible = "mediatek,mt2712-mmsys",
322 { .compatible = "mediatek,mt8167-mmsys",
324 { .compatible = "mediatek,mt8173-mmsys",
326 { .compatible = "mediatek,mt8183-mmsys",
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/kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
[all …]
Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/drivers/pwm/
Dpwm-mtk-disp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
15 #include <linux/pwm.h>
25 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
60 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
69 static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in mtk_disp_pwm_config() argument
77 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_config()
79 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_config()
83 err = clk_prepare_enable(mdp->clk_mm); in mtk_disp_pwm_config()
85 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_config()
[all …]
/kernel/linux/linux-6.6/drivers/pwm/
Dpwm-mtk-disp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
15 #include <linux/pwm.h>
25 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
61 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
70 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mtk_disp_pwm_apply() argument
78 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
79 return -EINVAL; in mtk_disp_pwm_apply()
81 if (!state->enabled && mdp->enabled) { in mtk_disp_pwm_apply()
83 mdp->data->enable_mask, 0x0); in mtk_disp_pwm_apply()
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