Searched +full:non +full:- +full:cacheable (Results 1 – 25 of 271) sorted by relevance
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | memory.json | 5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St…
6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older …
12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee…
18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed…
24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full."
90 …esses, although these are generally rare. Each increment represents an eight-byte access, although…
197 "BriefDescription": "Total Page Table Walks on I-side.",
215 "BriefDescription": "Total Page Table Walks on D-side.",
262 … the processor core. Software PREFETCH instruction saw a match on an already-allocated miss reques…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
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| D | memory.json | 5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St…
6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older …
12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee…
18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed…
24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full."
90 …esses, although these are generally rare. Each increment represents an eight-byte access, although…
197 "BriefDescription": "Total Page Table Walks on I-side.",
215 "BriefDescription": "Total Page Table Walks on D-side.",
262 … the processor core. Software PREFETCH instruction saw a match on an already-allocated miss reques…
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
14 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
32 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
40 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
70 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
73 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
89 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
145 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
153 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
[all …]
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| /kernel/linux/linux-6.6/arch/riscv/include/asm/ |
| D | pgtable-64.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define PGDIR_MASK (~(PGDIR_SIZE - 1))
27 /* p4d is folded into pgd in case of 4-level page table */
34 #define P4D_MASK (~(P4D_SIZE - 1))
36 /* pud is folded into pgd in case of 3-level page table */
39 #define PUD_MASK (~(PUD_SIZE - 1))
44 #define PMD_MASK (~(PMD_SIZE - 1))
100 for (order = NAPOT_ORDER_MAX - 1; \
101 order >= NAPOT_CONT_ORDER_BASE; order--)
106 #define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL))
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | memory.json | 30 "PublicDescription": "External memory request to non-cacheable memory",
33 "BriefDescription": "External memory request to non-cacheable memory"
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore.json | 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ…
68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req…
79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo…
80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem…
91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore.json | 19 "BriefDescription": "A snoop invalidates a non-modified line in some processor core.",
20 "PublicDescription": "A snoop invalidates a non-modified line in some processor core.",
31 "BriefDescription": "A snoop hits a non-modified line in some processor core.",
32 "PublicDescription": "A snoop hits a non-modified line in some processor core.",
67 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop requ…
68 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop req…
79 …"BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memo…
80 …"PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core mem…
91 "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
92 "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.",
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | cache.json | 13 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
21 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
31 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
47 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
55 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
84 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
87 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
103 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
108 …"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MI…
111 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
22 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
103 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
284 "BriefDescription": "Core-originated cacheable demand requests missed L3",
287 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la…
292 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
295 …"PublicDescription": "This event counts core-originated cacheable demand requests that refer to th…
300 …ription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core c…
306 …ts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core …
322 …on": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core …
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pmem/ |
| D | pmem-region.txt | 1 Device-tree bindings for persistent memory regions
2 -----------------------------------------------------
6 a) Usable as main system memory (i.e. cacheable), and
16 -----------------------------
19 - compatible = "pmem-region"
21 - reg = <base, size>;
25 (i.e cacheable).
33 - Any relevant NUMA assocativity properties for the target platform.
35 - volatile; This property indicates that this region is actually
36 backed by non-persistent memory. This lets the OS know that it
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pmem/ |
| D | pmem-region.txt | 1 Device-tree bindings for persistent memory regions
2 -----------------------------------------------------
6 a) Usable as main system memory (i.e. cacheable), and
16 -----------------------------
19 - compatible = "pmem-region"
21 - reg = <base, size>;
25 (i.e cacheable).
33 - Any relevant NUMA associativity properties for the target platform.
35 - volatile; This property indicates that this region is actually
36 backed by non-persistent memory. This lets the OS know that it
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/snowridgex/ |
| D | cache.json | 21 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
56 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
59 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C…
64 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
67 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca…
72 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
75 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
80 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
83 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
104 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| D | cache.json | 21 … The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L…
56 …"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts o…
59 …"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level C…
64 …"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on…
67 …"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Ca…
72 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
75 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
80 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
83 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",
104 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
14 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
32 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
40 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
70 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
73 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
89 …quests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses t…
129 …ublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss exc…
134 "BriefDescription": "Read requests with true-miss in L2 cache",
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | cache.json | 6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
22 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
103 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
284 "BriefDescription": "Core-originated cacheable demand requests missed L3",
287 …"PublicDescription": "This event counts core-originated cacheable demand requests that miss the la…
292 "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
295 …"PublicDescription": "This event counts core-originated cacheable demand requests that refer to th…
300 …ription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core c…
306 …ts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core …
322 …on": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core …
[all …]
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| /kernel/linux/linux-6.6/tools/perf/pmu-events/arch/x86/meteorlake/ |
| D | cache.json | 14 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
23 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
34 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
43 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
52 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
86 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
89 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
98 …"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excl…
113 …"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MIS…
116 …ublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss exc…
[all …]
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
57 #define DCACHE_SIZE 0x8000 /* data - 32k */
61 #define ICACHE_SIZE 0x2000 /* instruction - 8k */
62 #define DCACHE_SIZE 0x2000 /* data - 8k */
68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
[all …]
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| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
57 #define DCACHE_SIZE 0x8000 /* data - 32k */
61 #define ICACHE_SIZE 0x2000 /* instruction - 8k */
62 #define DCACHE_SIZE 0x2000 /* data - 8k */
68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
[all …]
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| /kernel/linux/linux-5.10/tools/arch/powerpc/include/asm/ |
| D | barrier.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * providing an ordering (separately) for (a) cacheable stores and (b)
16 * loads and stores to non-cacheable memory (e.g. I/O devices).
|
| /kernel/linux/linux-6.6/tools/arch/powerpc/include/asm/ |
| D | barrier.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * providing an ordering (separately) for (a) cacheable stores and (b)
16 * loads and stores to non-cacheable memory (e.g. I/O devices).
|
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