| /kernel/linux/linux-5.10/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
8 memory devices like
14 * Pseudo-SRAM devices
23 GPMC has certain timings that has to be programmed for proper
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
26 be translated to the form gpmc can understand. The way it has to be
27 translated depends on the connected peripheral. Also there is a
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| /kernel/linux/linux-6.6/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPMC (General Purpose Memory Controller)
7 GPMC is an unified memory controller dedicated to interfacing external
8 memory devices like
14 * Pseudo-SRAM devices
23 GPMC has certain timings that has to be programmed for proper
24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
26 be translated to the form gpmc can understand. The way it has to be
27 translated depends on the connected peripheral. Also there is a
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | mc-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
14 and there can be multiple peripherals attached to a controller. All
20 - Marek Vasut <marex@denx.de>
26 bank-width:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
23 System MMUs are in many to one relation with peripheral devices, i.e. single
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
5 - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
6 "microchip,sama7g5-dma" or
7 "microchip,sam9x7-dma", "atmel,sama5d4-dma".
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Should contain DMA interrupt.
10 - #dma-cells: Must be <1>, used to represent the number of integer cells in
12 - The 1st cell specifies the channel configuration register:
13 - bit 13: SIF, source interface identifier, used to get the memory
15 - bit 14: DIF, destination interface identifier, used to get the peripheral
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 1 * Atmel Extensible Direct Memory Access Controller (XDMAC)
5 - compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
6 - reg: Should contain DMA registers location and length.
7 - interrupts: Should contain DMA interrupt.
8 - #dma-cells: Must be <1>, used to represent the number of integer cells in
10 - The 1st cell specifies the channel configuration register:
11 - bit 13: SIF, source interface identifier, used to get the memory
13 - bit 14: DIF, destination interface identifier, used to get the peripheral
15 - bit 30-24: PERID, peripheral identifier.
19 dma1: dma-controller@f0004000 {
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
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| D | fsl-imx-sdma.txt | 1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
4 - compatible : Should be one of
5 "fsl,imx25-sdma"
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8 "fsl,imx51-sdma"
9 "fsl,imx53-sdma"
10 "fsl,imx6q-sdma"
11 "fsl,imx7d-sdma"
12 "fsl,imx8mq-sdma"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17 System MMU is an IOMMU and supports identical translation table format to
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
23 System MMUs are in many to one relation with peripheral devices, i.e. single
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/ |
| D | sm501.rst | 15 ----
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
38 the specific set of resources that peripheral requires in order to
41 The centralised memory allocation allows the driver to ensure that the
42 maximum possible resource allocation can be made to the video subsystem
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | sm501.rst | 15 ----
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
30 system provides enough features to support the drivers without the
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
38 the specific set of resources that peripheral requires in order to
41 The centralised memory allocation allows the driver to ensure that the
42 maximum possible resource allocation can be made to the video subsystem
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| /kernel/linux/linux-5.10/drivers/gpu/drm/ |
| D | drm_mipi_dsi.c | 4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
43 * These functions contain some common logic and helpers to deal with MIPI DSI
59 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
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| /kernel/linux/linux-5.10/arch/mips/include/asm/txx9/ |
| D | dmac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct txx9dmac_platform_data - Controller configuration parameters
24 * struct txx9dmac_chan_platform_data - Channel configuration parameters
32 * struct txx9dmac_slave - Controller-specific information about a slave
34 * memory-to-peripheral transfers
36 * peripheral-to-memory transfers
37 * @reg_width: peripheral register width
|
| /kernel/linux/linux-6.6/arch/mips/include/asm/txx9/ |
| D | dmac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 * struct txx9dmac_platform_data - Controller configuration parameters
24 * struct txx9dmac_chan_platform_data - Channel configuration parameters
32 * struct txx9dmac_slave - Controller-specific information about a slave
34 * memory-to-peripheral transfers
36 * peripheral-to-memory transfers
37 * @reg_width: peripheral register width
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/ |
| D | drm_mipi_dsi.c | 4 * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
44 * These functions contain some common logic and helpers to deal with MIPI DSI
60 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
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| /kernel/linux/linux-5.10/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 used to offload memory copies in the network stack and
103 tristate "Analog Devices AXI-DMAC DMA support"
109 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
125 has the capability to offload memcpy, xor and pq computation
129 bool "ST-Ericsson COH901318 DMA support"
133 Enable support for ST-Ericsson COH 901 318 DMA.
148 If you have a board based on such a SoC and wish to use DMA for
152 tristate "SA-11x0 DMA support"
157 Support the DMA engine found on Intel StrongARM SA-1100 and
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| /kernel/linux/linux-6.6/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 used to offload memory copies in the network stack and
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
134 has the capability to offload memcpy, xor and pq computation
150 If you have a board based on such a SoC and wish to use DMA for
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
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| /kernel/linux/linux-5.10/drivers/firmware/ |
| D | qcom_scm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
17 #include <linux/reset-controller.h>
18 #include <linux/arm-smccc.h>
87 ret = clk_prepare_enable(__scm->core_clk); in qcom_scm_clk_enable()
91 ret = clk_prepare_enable(__scm->iface_clk); in qcom_scm_clk_enable()
95 ret = clk_prepare_enable(__scm->bus_clk); in qcom_scm_clk_enable()
102 clk_disable_unprepare(__scm->iface_clk); in qcom_scm_clk_enable()
104 clk_disable_unprepare(__scm->core_clk); in qcom_scm_clk_enable()
111 clk_disable_unprepare(__scm->core_clk); in qcom_scm_clk_disable()
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
28 Say Y if you want to support higher CPU frequencies on MSM8916
37 Say Y if you want to support CPU frequency scaling on devices
46 Say Y if you want to support CPU clock scaling using CPUfreq
55 managing the shared SoC resources in order to keep the lowest power
57 memory and accepts clock requests, aggregates the requests and turns
59 Say Y if you want to support the clocks exposed by the RPM on
68 managing the shared SoC resources in order to keep the lowest power
70 memory and accepts clock requests, aggregates the requests and turns
72 Say Y if you want to support the clocks exposed by the RPM on
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/ |
| D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
19 - Mark Brown <broonie@kernel.org>
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| /kernel/linux/linux-6.6/drivers/firmware/ |
| D | qcom_scm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include <linux/reset-controller.h>
22 #include <linux/arm-smccc.h>
38 /* control access to the interconnect path */
82 ret = clk_prepare_enable(__scm->core_clk); in qcom_scm_clk_enable()
86 ret = clk_prepare_enable(__scm->iface_clk); in qcom_scm_clk_enable()
90 ret = clk_prepare_enable(__scm->bus_clk); in qcom_scm_clk_enable()
97 clk_disable_unprepare(__scm->iface_clk); in qcom_scm_clk_enable()
99 clk_disable_unprepare(__scm->core_clk); in qcom_scm_clk_enable()
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| /kernel/linux/linux-5.10/arch/powerpc/platforms/chrp/ |
| D | gg2.h | 2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
11 * This file is subject to the terms and conditions of the GNU General Public
20 * Memory Map (CHRP mode)
23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
|
| /kernel/linux/linux-6.6/arch/powerpc/platforms/chrp/ |
| D | gg2.h | 2 * include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
11 * This file is subject to the terms and conditions of the GNU General Public
20 * Memory Map (CHRP mode)
23 #define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
24 #define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
25 #define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
24 Primary mode of the bxCAN peripheral is only relevant if the chip has
27 Not to be used if the peripheral is in single CAN configuration.
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