Searched full:pl1 (Results 1 – 25 of 69) sorted by relevance
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| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-driver-intel-i915-hwmon | 13 Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
17 exceeds this limit. A read value of 0 means that the PL1
35 Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
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| D | sysfs-platform-asus-wmi | 135 Set the Package Power Target total of CPU: PL1 on Intel, SPL on AMD.
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/allwinner/ |
| D | sunxi-bananapi-m2-plus-v1.2.dtsi | 22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| D | sun8i-h2-plus-bananapi-m2-zero.dts | 71 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| D | sun8i-a23-a33.dtsi | 823 pins = "PL0", "PL1";
829 pins = "PL0", "PL1";
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | sunxi-bananapi-m2-plus-v1.2.dtsi | 22 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| D | sun8i-h2-plus-bananapi-m2-zero.dts | 59 gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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| D | sun8i-a23-a33.dtsi | 818 pins = "PL0", "PL1";
824 pins = "PL0", "PL1";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra210-pinmux.txt | 108 pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,
131 pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
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| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | booting.rst | 222 the HYP mode configuration in addition to the ordinary PL1 (privileged
224 hypervisor must be disabled, and PL1 access must be granted for all
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| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | booting.rst | 222 the HYP mode configuration in addition to the ordinary PL1 (privileged
224 hypervisor must be disabled, and PL1 access must be granted for all
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| D | i915_hwmon.c | 357 * HW allows arbitrary PL1 limits to be set but silently clamps these values to
359 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
369 /* Check if PL1 limit is disabled */ in hwm_power_max_read()
429 /* Disable PL1 limit and verify, because the limit cannot be disabled on all platforms */ in hwm_power_max_write()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra210-pinmux.yaml | 56 pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
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| /kernel/linux/linux-5.10/arch/arm/kernel/ |
| D | head-nommu.S | 290 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
302 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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| D | hyp-stub.S | 144 @ make CNTP_* and CNTPCT accessible from PL1
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| /kernel/linux/linux-6.6/arch/arm/kernel/ |
| D | head-nommu.S | 291 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
303 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
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| D | hyp-stub.S | 146 @ make CNTP_* and CNTPCT accessible from PL1
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-h6-beelink-gs1.dts | 283 * PL0 and PL1 are used for PMIC I2C
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| D | sun50i-a100.dtsi | 295 pins = "PL0", "PL1";
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| /kernel/liteos_a/arch/arm/arm/include/ |
| D | los_hw_cpu.h | 129 #define TPIDRPRW CP15_REG(c13, 0, c0, 4) /* PL1 only Thread ID Register */
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| /kernel/linux/linux-5.10/tools/arch/arm/include/uapi/asm/ |
| D | kvm.h | 179 /* PL1 Physical Timer Registers */
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| /kernel/linux/linux-6.6/tools/arch/arm/include/uapi/asm/ |
| D | kvm.h | 179 /* PL1 Physical Timer Registers */
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/allwinner/ |
| D | sun50i-h616.dtsi | 699 pins = "PL0", "PL1";
704 pins = "PL0", "PL1";
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| D | sun50i-a100.dtsi | 319 pins = "PL0", "PL1";
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| /kernel/linux/linux-6.6/arch/parisc/kernel/ |
| D | entry.S | 511 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
521 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
600 * to type field and _PAGE_READ goes to top bit of PL1
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