| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 159 pll0: pll0@800 {
164 clock-output-names = "pll0", "pll0-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 160 pll0: pll0@800 {
165 clock-output-names = "pll0", "pll0-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | microchip,mpfs-ccc.yaml | 24 - description: PLL0's control registers
35 - description: PLL0's refclk0
36 - description: PLL0's refclk1
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| D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
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| /kernel/linux/linux-6.6/drivers/clk/mxs/ |
| D | clk-imx28.c | 127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mxs/ |
| D | clk-imx28.c | 127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
176 clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1); in mx28_clocks_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 14 * - PLL0 (1 Ghz)
15 * - PPv2 core (1/3 PLL0)
16 * - x2 Core (1/2 PLL0)
18 * - SDIO (2/5 PLL0)
22 * - 2/5 PLL0
247 /* Register the PLL0 which is the root of the hw tree */ in cp110_syscon_common_probe()
248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); in cp110_syscon_common_probe()
258 /* PPv2 is PLL0/3 */ in cp110_syscon_common_probe()
268 /* X2CORE clock is PLL0/2 */ in cp110_syscon_common_probe()
289 /* NAND can be either PLL0/2.5 or core clock */ in cp110_syscon_common_probe()
[all …]
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| /kernel/linux/linux-5.10/drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
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| /kernel/linux/linux-6.6/drivers/bcma/ |
| D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
[all …]
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| /kernel/linux/linux-5.10/drivers/soc/kendryte/ |
| D | k210-sysctl.c | 136 u32 clksel0, pll0; in k210_sysctl_clk_recalc_rate() local
141 * Otherwise, use PLL0 frequency with a frequency divisor. in k210_sysctl_clk_recalc_rate()
148 * Get PLL0 frequency: in k210_sysctl_clk_recalc_rate()
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
152 clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); in k210_sysctl_clk_recalc_rate()
153 clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); in k210_sysctl_clk_recalc_rate()
154 clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); in k210_sysctl_clk_recalc_rate()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
|
| /kernel/linux/linux-6.6/include/linux/firmware/imx/svc/ |
| D | pm.h | 80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
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| /kernel/linux/linux-5.10/include/linux/firmware/imx/svc/ |
| D | pm.h | 80 #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-k210.c | 300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
301 * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
340 * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
398 * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and in k210_pll_enable_hw()
461 * stop working. This is especially important for pll0, the indirect in k210_pll_disable()
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
577 ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops); in k210_register_plls()
579 pr_err("%pOFP: register PLL0 failed\n", np); in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
645 * ACLK has IN0 and PLL0 as parents.
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | stih407-clock.dtsi | 77 compatible = "st,clkgen-pll0";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| D | stih410-clock.dtsi | 77 compatible = "st,clkgen-pll0";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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| /kernel/linux/linux-6.6/drivers/clk/ingenic/ |
| D | jz4760-cgu.c | 93 "pll0", CGU_CLK_PLL,
117 /* TODO: PLL1 can depend on PLL0 */
212 /* Those divided clocks can connect to PLL0 or PLL1 */
254 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
280 /* Those divided clocks can connect to EXT or PLL0 */
294 /* These divided clock can connect to PLL0 only */
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| /kernel/linux/linux-6.6/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
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| /kernel/linux/linux-5.10/arch/arc/boot/dts/ |
| D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/st/ |
| D | stih407-clock.dtsi | 70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
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| D | stih418-clock.dtsi | 75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
|