| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
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| D | qoriq-clock.txt | 167 pll1: pll1@820 {
172 clock-output-names = "pll1", "pll1-div2";
179 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
180 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
188 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
189 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1-clk";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
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| D | qoriq-clock.txt | 168 pll1: pll1@820 {
173 clock-output-names = "pll1", "pll1-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| D | microchip,mpfs-ccc.yaml | 25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
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| D | silabs,si5351.txt | 82 /* connect xtal input as source of pll0 and pll1 */
105 * - pll1 as clock source of multisynth1
107 * - multisynth1 can change pll1
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| /kernel/linux/linux-6.6/include/linux/iio/frequency/ |
| D | ad9523.h | 117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
160 /* PLL1 Setting */
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| /kernel/linux/linux-5.10/include/linux/iio/frequency/ |
| D | ad9523.h | 117 * @refa_r_div: PLL1 10-bit REFA R divider.
118 * @refb_r_div: PLL1 10-bit REFB R divider.
119 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
120 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
160 /* PLL1 Setting */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
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| /kernel/linux/linux-5.10/drivers/clk/renesas/ |
| D | clk-sh73a0.c | 49 { "m3", "pll1", CPG_FRQCRA, 12 },
50 { "b", "pll1", CPG_FRQCRA, 8 },
51 { "m1", "pll1", CPG_FRQCRA, 4 },
52 { "m2", "pll1", CPG_FRQCRA, 0 },
53 { "zx", "pll1", CPG_FRQCRB, 12 },
54 { "hp", "pll1", CPG_FRQCRB, 4 },
113 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
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| /kernel/linux/linux-6.6/drivers/clk/renesas/ |
| D | clk-sh73a0.c | 48 { "m3", "pll1", CPG_FRQCRA, 12 },
49 { "b", "pll1", CPG_FRQCRA, 8 },
50 { "m1", "pll1", CPG_FRQCRA, 4 },
51 { "m2", "pll1", CPG_FRQCRA, 0 },
52 { "zx", "pll1", CPG_FRQCRB, 12 },
53 { "hp", "pll1", CPG_FRQCRB, 4 },
112 /* handle CFG bit for PLL1 and PLL2 */ in sh73a0_cpg_register_clock()
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-pxa910.c | 107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
108 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
110 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
146 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa910_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa910_clk_init()
154 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa910_clk_init()
158 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa910_clk_init()
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| D | clk-pxa168.c | 102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
103 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
105 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
141 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", in pxa168_clk_init()
145 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", in pxa168_clk_init()
149 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", in pxa168_clk_init()
153 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", in pxa168_clk_init()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
214 /* model specific additions to generic pll1 and pll2 set up above */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /kernel/linux/linux-5.10/arch/c6x/platforms/ |
| D | plldata.c | 26 /* Default input for PLL1 */
38 .name = "pll1",
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
193 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
233 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
289 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
338 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-pll.txt | 15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-k210.c | 300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
302 * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
582 ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops); in k210_register_plls()
584 pr_err("%pOFP: register PLL1 failed\n", np); in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
998 * Enable PLL1 to be able to use the AI SRAM.
1002 struct k210_pll pll1; in k210_clk_early_init() local
1007 /* Startup PLL1 to enable the aisram bank for general memory use */ in k210_clk_early_init()
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-ep93xx/ |
| D | clock.c | 40 "pll1",
555 /* Determine the bootloader configured pll1 rate */ in ep93xx_clock_init()
562 hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate); in ep93xx_clock_init()
563 clk_hw_register_clkdev(hw, NULL, "pll1"); in ep93xx_clock_init()
565 /* Initialize the pll1 derived clocks */ in ep93xx_clock_init()
570 hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div); in ep93xx_clock_init()
572 hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div); in ep93xx_clock_init()
640 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", in ep93xx_clock_init()
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| /kernel/linux/linux-6.6/Documentation/arch/arm/sunxi/ |
| D | clocks.rst | 20 PLL1
31 PLL1 |
|
| /kernel/linux/linux-5.10/Documentation/arm/sunxi/ |
| D | clocks.rst | 20 PLL1
31 PLL1 |
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 285 u32 *pll1, u32 *pll2) in get_pll_config() argument
293 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
300 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
316 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
325 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
|