| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soundwire/ |
| D | qcom,soundwire.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_nsp_eth.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
77 __le64 control; member
121 dst[ETH_ALEN - i - 1] = src[i]; in nfp_eth_copy_mac_reverse()
132 port = le64_to_cpu(src->port); in nfp_eth_port_translate()
133 state = le64_to_cpu(src->state); in nfp_eth_port_translate()
135 dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); in nfp_eth_port_translate()
136 dst->index = index; in nfp_eth_port_translate()
137 dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
138 dst->base = index % NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_nsp_eth.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
80 __le64 control; member
124 dst[ETH_ALEN - i - 1] = src[i]; in nfp_eth_copy_mac_reverse()
135 port = le64_to_cpu(src->port); in nfp_eth_port_translate()
136 state = le64_to_cpu(src->state); in nfp_eth_port_translate()
138 dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); in nfp_eth_port_translate()
139 dst->index = index; in nfp_eth_port_translate()
140 dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
141 dst->base = index % NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/dsa/mv88e6xxx/ |
| D | chip.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
24 /* PVT limits for 4-bit port and 5-bit switch */
117 /* Mark certain ports as invalid. This is required for example for the
118 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
119 * ports 2-4 are not routet to pins.
122 /* Multi-chip Addressing Mode.
124 * when it is non-zero, and use indirect access to internal registers.
127 /* Dual-chip Addressing Mode
276 /* Handles automatic disabling and re-enabling of the PHY
[all …]
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| D | port.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
23 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_read()
31 int addr = chip->info->port_base_addr + port; in mv88e6xxx_port_write()
59 /* Offset 0x01: MAC (or PCS or Physical) Control Register
61 * Link, Duplex and Flow Control have one force bit, one value bit.
102 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port, in mv88e6xxx_port_set_rgmii_delay()
113 return -EOPNOTSUPP; in mv88e6352_port_set_rgmii_delay()
122 return -EOPNOTSUPP; in mv88e6390_port_set_rgmii_delay()
151 return -EINVAL; in mv88e6xxx_port_set_link()
[all …]
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| D | chip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88e6xxx Ethernet switch single-chip support
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { in assert_reg_lock()
48 dev_err(chip->dev, "Switch registers lock not held!\n"); in assert_reg_lock()
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", in mv88e6xxx_read()
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", in mv88e6xxx_write()
104 dev_err(chip->dev, "Timeout while waiting for switch\n"); in mv88e6xxx_wait_mask()
105 return -ETIMEDOUT; in mv88e6xxx_wait_mask()
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, in mv88e6xxx_default_mdio_bus()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
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| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
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| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soundwire/ |
| D | qcom,sdw.txt | 7 - compatible:
10 Definition: must be "qcom,soundwire-v<MAJOR>.<MINOR>.<STEP>",
12 "qcom,soundwire-v1.3.0"
13 "qcom,soundwire-v1.5.0"
14 "qcom,soundwire-v1.5.1"
15 "qcom,soundwire-v1.6.0"
16 - reg:
18 Value type: <prop-encoded-array>
22 - interrupts:
24 Value type: <prop-encoded-array>
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
[all …]
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| /kernel/linux/linux-6.6/drivers/thunderbolt/ |
| D | switch.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
75 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
76 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
77 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
80 st->status = status; in nvm_set_auth_status()
[all …]
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| D | acpi.c | 1 // SPDX-License-Identifier: GPL-2.0
26 fwnode = fwnode_find_reference(acpi_fwnode_handle(adev), "usb4-host-interface", 0); in tb_acpi_add_link()
31 if (dev_fwnode(&nhi->pdev->dev) != fwnode) in tb_acpi_add_link()
37 * bound so the USB3 SuperSpeed ports are not yet created. in tb_acpi_add_link()
49 * SuperSpeed ports have this property and they are not power in tb_acpi_add_link()
54 dev = dev->parent; in tb_acpi_add_link()
65 if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI || in tb_acpi_add_link()
78 pm_runtime_get_sync(&pdev->dev); in tb_acpi_add_link()
80 link = device_link_add(&pdev->dev, &nhi->pdev->dev, in tb_acpi_add_link()
85 dev_dbg(&nhi->pdev->dev, "created link from %s\n", in tb_acpi_add_link()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra124-xusb-padctl.txt | 5 signals) which connect directly to pins/pads on the SoC package. Each lane
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-host.txt | 4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
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| D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/tegra/ |
| D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/connector/ |
| D | usb-connector.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
[all …]
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| /kernel/linux/linux-5.10/drivers/thunderbolt/ |
| D | switch.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
11 #include <linux/nvmem-provider.h>
47 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
62 *status = st ? st->status : 0; in nvm_get_auth_status()
69 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
80 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
81 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
82 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
85 st->status = status; in nvm_set_auth_status()
[all …]
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| /kernel/linux/linux-6.6/drivers/usb/host/ |
| D | xhci-hub.c | 1 // SPDX-License-Identifier: GPL-2.0
17 #include "xhci-trace.h"
23 /* Default sublink speed attribute of each lane */
53 bos->bLength = USB_DT_BOS_SIZE; in xhci_create_usb3x_bos_desc()
54 bos->bDescriptorType = USB_DT_BOS; in xhci_create_usb3x_bos_desc()
55 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + in xhci_create_usb3x_bos_desc()
57 bos->bNumDeviceCaps = 1; in xhci_create_usb3x_bos_desc()
60 for (i = 0; i < xhci->num_port_caps; i++) { in xhci_create_usb3x_bos_desc()
61 u8 major = xhci->port_caps[i].maj_rev; in xhci_create_usb3x_bos_desc()
62 u8 minor = xhci->port_caps[i].min_rev; in xhci_create_usb3x_bos_desc()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/ |
| D | fsl,fman-dtsec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | video-interfaces.txt | 4 ---------------
20 ports {
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
40 All 'port' nodes can be grouped under optional 'ports' node, which allows to
41 specify #address-cells, #size-cells properties independently for the 'port'
44 Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
53 a device is partitioned into multiple data busses, e.g. 16-bit input port
54 divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
[all …]
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