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12

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/
Drenesas,dw-hdmi.txt1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall contain one or more of
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/renesas/rcar-du/
Drcar_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Gen3 HDMI PHY
41 rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in rcar_hdmi_mode_valid() argument
49 if (mode->clock > 297000) in rcar_hdmi_mode_valid()
55 static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, in rcar_hdmi_phy_configure() argument
60 for (; params->mpixelclock != ~0UL; ++params) { in rcar_hdmi_phy_configure()
61 if (mpixelclock <= params->mpixelclock) in rcar_hdmi_phy_configure()
65 if (params->mpixelclock == ~0UL) in rcar_hdmi_phy_configure()
66 return -EINVAL; in rcar_hdmi_phy_configure()
68 dw_hdmi_phy_i2c_write(hdmi, params->opmode_div, in rcar_hdmi_phy_configure()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 tristate "DRM Support for R-Car Display Unit"
11 Choose this option if you have an R-Car chipset.
12 If M is selected the module will be called rcar-du-drm.
15 bool "R-Car DU Color Management Module (CMM) Support"
19 Enable support for R-Car Color Management Module (CMM).
26 tristate "R-Car Gen3 and RZ/G2 DU HDMI Encoder Support"
31 Enable support for R-Car Gen3 or RZ/G2 internal HDMI encoder.
34 bool "R-Car DU LVDS Encoder Support"
39 Enable support for the R-Car Display Unit embedded LVDS encoders.
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rcar-du/
Drcar_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Gen3 HDMI PHY
41 rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in rcar_hdmi_mode_valid() argument
49 if (mode->clock > 297000) in rcar_hdmi_mode_valid()
55 static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, in rcar_hdmi_phy_configure() argument
60 for (; params->mpixelclock != ~0UL; ++params) { in rcar_hdmi_phy_configure()
61 if (mpixelclock <= params->mpixelclock) in rcar_hdmi_phy_configure()
65 if (params->mpixelclock == ~0UL) in rcar_hdmi_phy_configure()
66 return -EINVAL; in rcar_hdmi_phy_configure()
68 dw_hdmi_phy_i2c_write(hdmi, params->opmode_div, in rcar_hdmi_phy_configure()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 tristate "DRM Support for R-Car Display Unit"
12 Choose this option if you have an R-Car chipset.
13 If M is selected the module will be called rcar-du-drm.
16 bool "R-Car DU Color Management Module (CMM) Support"
20 Enable support for R-Car Color Management Module (CMM).
27 tristate "R-Car Gen3 and RZ/G2 DU HDMI Encoder Support"
31 Enable support for R-Car Gen3 or RZ/G2 internal HDMI encoder.
34 bool "R-Car DU LVDS Encoder Support"
38 Enable support for the R-Car Display Unit embedded LVDS encoders.
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/bridge/
Drenesas,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
22 - enum:
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
Dr8a774b1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774b1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
[all …]
Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
Dr8a774b1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774b1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <0>;
[all …]
Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
[all …]
Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
19 #address-cells = <2>;
20 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
[all …]
Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
10 * SSI-AK4613
11 * aplay -D plughw:0,0 xxx.wav
12 * arecord -D plughw:0,0 xxx.wav
13 * SSI-HDMI
14 * aplay -D plughw:0,1 xxx.wav
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/input/input.h>
21 model = "Renesas R-Car Gen3 ULCB board";
[all …]
/kernel/linux/linux-6.6/drivers/clk/renesas/
Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
124 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
/kernel/linux/linux-5.10/drivers/clk/renesas/
Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
120 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
128 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
129 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
[all …]
Dr8a774a1-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7796-cpg-mssr.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
108 DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
121 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
131 DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S3D1),
132 DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S3D1),
[all …]
Dr8a77965-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
17 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
125 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
135 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
136 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
[all …]

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