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/kernel/linux/linux-5.10/include/video/
Ds1d13xxxfb.h20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
[all …]
/kernel/linux/linux-6.6/include/video/
Ds1d13xxxfb.h20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
[all …]
/kernel/linux/linux-6.6/drivers/pinctrl/
Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
22 #define PIO_CODR 0x34 /* Clear Output Data Register */
23 #define PIO_ODSR 0x38 /* Output Data Status Register */
24 #define PIO_PDSR 0x3c /* Pin Data Status Register */
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
22 #define PIO_CODR 0x34 /* Clear Output Data Register */
23 #define PIO_ODSR 0x38 /* Output Data Status Register */
24 #define PIO_PDSR 0x3c /* Pin Data Status Register */
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/deprecated/atmel/
Datmel-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
60 /* ISC Clock Enable Register */
63 /* ISC Clock Disable Register */
66 /* ISC Clock Status Register */
72 /* ISC Clock Configuration Register */
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/microchip/
Dmicrochip-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
60 /* ISC Clock Enable Register */
63 /* ISC Clock Disable Register */
66 /* ISC Clock Status Register */
72 /* ISC Clock Configuration Register */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-sa1100/
Djornada720.c56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-sa1100/
Djornada720.c56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/kernel/linux/linux-6.6/include/linux/fsl/
Dguts.h3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
[all …]
/kernel/linux/linux-5.10/include/linux/fsl/
Dguts.h3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
[all …]
/kernel/linux/linux-5.10/drivers/crypto/ux500/cryp/
Dcryp_irqp.h20 * 00h | CRYP_CR | Configuration register
22 * 04h | CRYP_SR | Status register
24 * 08h | CRYP_DIN | Data In register
26 * 0ch | CRYP_DOUT | Data out register
28 * 10h | CRYP_DMACR | DMA control register
41 * Refer data structure for other register map
46 * @cr - Configuration register
47 * @status - Status register
48 * @din - Data input register
49 * @din_size - Data input size register
[all …]
/kernel/linux/linux-6.6/include/soc/fsl/qe/
Dimmap_qe.h24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
56 __be32 cecr; /* QE command register */
57 __be32 ceccr; /* QE controller configuration register */
58 __be32 cecdr; /* QE command data register */
60 __be16 ceter; /* QE timer event register */
62 __be16 cetmr; /* QE timers mask register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
[all …]
/kernel/linux/linux-5.10/include/soc/fsl/qe/
Dimmap_qe.h23 __be32 iadd; /* I-RAM Address Register */
24 __be32 idata; /* I-RAM Data Register */
26 __be32 iready; /* I-RAM Ready Register */
55 __be32 cecr; /* QE command register */
56 __be32 ceccr; /* QE controller configuration register */
57 __be32 cecdr; /* QE command data register */
59 __be16 ceter; /* QE timer event register */
61 __be16 cetmr; /* QE timers mask register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Drz-mtu3.h12 /* 8-bit shared register offsets macros */
13 #define RZ_MTU3_TSTRA 0x080 /* Timer start register A */
14 #define RZ_MTU3_TSTRB 0x880 /* Timer start register B */
16 /* 16-bit shared register offset macros */
17 #define RZ_MTU3_TDDRA 0x016 /* Timer dead time data register A */
18 #define RZ_MTU3_TDDRB 0x816 /* Timer dead time data register B */
19 #define RZ_MTU3_TCDRA 0x014 /* Timer cycle data register A */
20 #define RZ_MTU3_TCDRB 0x814 /* Timer cycle data register B */
21 #define RZ_MTU3_TCBRA 0x022 /* Timer cycle buffer register A */
22 #define RZ_MTU3_TCBRB 0x822 /* Timer cycle buffer register B */
[all …]
Dtps65910.h126 * List of register bitfields for component TPS65910
142 /*Register BCK1 (0x80) register.RegisterDescription */
147 /*Register BCK2 (0x80) register.RegisterDescription */
152 /*Register BCK3 (0x80) register.RegisterDescription */
157 /*Register BCK4 (0x80) register.RegisterDescription */
162 /*Register BCK5 (0x80) register.RegisterDescription */
167 /*Register PUADEN (0x80) register.RegisterDescription */
186 /*Register REF (0x80) register.RegisterDescription */
193 /*Register VRTC (0x80) register.RegisterDescription */
200 /*Register VIO (0x80) register.RegisterDescription */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
Dpxa27x-udc.h11 #define UDCCR __REG(0x40600000) /* UDC Control Register */
50 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
51 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
59 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
87 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
88 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
106 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
116 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
117 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
118 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dpxa27x-udc.h9 #define UDCCR __REG(0x40600000) /* UDC Control Register */
48 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
49 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
57 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
85 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
86 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
104 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
114 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
115 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
116 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/atmel/
Datmel-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
43 /* ISC Parallel Front End Configuration 1 Register */
51 /* ISC Parallel Front End Configuration 2 Register */
59 /* ISC Clock Enable Register */
62 /* ISC Clock Disable Register */
65 /* ISC Clock Status Register */
71 /* ISC Clock Configuration Register */
[all …]
/kernel/linux/linux-6.6/arch/powerpc/include/asm/
Dmpic_msgr.h23 /* Get a message register
25 * @reg_num: the MPIC message register to get
27 * A pointer to the message register is returned. If
28 * the message register asked for is already in use, then
30 * with an actual message register, then ENODEV is returned.
31 * Successfully getting the register marks it as in use.
35 /* Relinquish a message register
37 * @msgr: the message register to return
39 * Disables the given message register and marks it as free.
41 * register is available to be acquired by a call to
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dmpic_msgr.h23 /* Get a message register
25 * @reg_num: the MPIC message register to get
27 * A pointer to the message register is returned. If
28 * the message register asked for is already in use, then
30 * with an actual message register, then ENODEV is returned.
31 * Successfully getting the register marks it as in use.
35 /* Relinquish a message register
37 * @msgr: the message register to return
39 * Disables the given message register and marks it as free.
41 * register is available to be acquired by a call to
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/da9052/
Dreg.h3 * Register declarations for DA9052 PMICs.
23 /* PARK REGISTER */
178 /* STATUS REGISTER A BITS */
188 /* STATUS REGISTER B BITS */
198 /* STATUS REGISTER C BITS */
208 /* STATUS REGISTER D BITS */
218 /* EVENT REGISTER A BITS */
228 /* EVENT REGISTER B BITS */
238 /* EVENT REGISTER C BITS */
248 /* EVENT REGISTER D BITS */
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/da9052/
Dreg.h3 * Register declarations for DA9052 PMICs.
23 /* PARK REGISTER */
178 /* STATUS REGISTER A BITS */
188 /* STATUS REGISTER B BITS */
198 /* STATUS REGISTER C BITS */
208 /* STATUS REGISTER D BITS */
218 /* EVENT REGISTER A BITS */
228 /* EVENT REGISTER B BITS */
238 /* EVENT REGISTER C BITS */
248 /* EVENT REGISTER D BITS */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-txcommon.h9 /* Register definitions for TX_P2 */
13 * Core Register Definitions
16 /* Device ID Low Byte Register */
19 /* Device ID High Byte Register */
22 /* Device version register */
25 /* Power Down Control Register */
34 /* Reset Control Register 1 */
45 /* Reset Control Register 2 */
51 /* Video Control Register 1 */
58 /* Video Control Register 2 */
[all …]

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