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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <atishp@rivosinc.com>
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
29 For information on the SBI specification see the section "Performance
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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/kernel/linux/linux-6.6/drivers/clocksource/
Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <clocksource/timer-riscv.h>
28 #include <asm/sbi.h>
93 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
94 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
96 ce->features |= CLOCK_EVT_FEAT_C3STOP; in riscv_timer_starting_cpu()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/kernel/linux/linux-5.10/drivers/clocksource/
Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
17 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <asm/sbi.h>
67 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
68 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
82 /* called directly from the low-level interrupt handler */
88 evdev->event_handler(evdev); in riscv_timer_interrupt()
116 child = of_get_compatible_child(n, "riscv,cpu-intc"); in riscv_timer_init_dt()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
165 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
188 32-bit free running decrementing counters.
242 bool "Integrator-AP timer driver" if COMPILE_TEST
245 Enables support for the Integrator-AP timer.
278 available on many OMAP-like platforms.
287 It has a 64-bit counter with update rate up to 1000MHz.
288 This counter is accessed via couple of 32-bit memory-mapped registers.
307 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
311 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/kernel/linux/linux-6.6/drivers/cpuidle/
Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
24 #include <asm/sbi.h>
51 data->available = true; in sbi_set_domain_state()
52 data->state = state; in sbi_set_domain_state()
59 return data->state; in sbi_get_domain_state()
66 data->available = false; in sbi_clear_domain_state()
73 return data->available; in sbi_is_domain_state_available()
114 u32 *states = data->states; in __sbi_enter_domain_idle_state()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
7 obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
8 obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
9 obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o
10 obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o
11 obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o
15 obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
16 obj-$(CONFIG_ARM_BIG_LITTLE_CPUIDLE) += cpuidle-big_little.o
17 obj-$(CONFIG_ARM_CLPS711X_CPUIDLE) += cpuidle-clps711x.o
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/kernel/linux/linux-6.6/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
168 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
175 depends on $(cc-option,-fpatchable-function-entry=8)
185 # VA_BITS - PAGE_SHIFT - 3
198 # set if we are running in S-mode and can use SBI calls
205 bool "MMU-based Paged Memory Management Support"
208 Select if you want MMU-based virtualised addressing space
280 This enables function pointer support for non-standard noncoherent
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/kernel/linux/linux-6.6/arch/riscv/kernel/
Dsbi-ipi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #define pr_fmt(fmt) "riscv: " fmt
14 #include <asm/sbi.h>
69 * via generic IPI-Mux in sbi_ipi_init()
72 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
76 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/sbi.h>
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
36 return -ENODEV; in riscv_of_processor_hartid()
44 return -ENODEV; in riscv_of_processor_hartid()
53 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
55 return -ENODEV; in riscv_early_of_processor_hartid()
61 return -ENODEV; in riscv_early_of_processor_hartid()
66 return -ENODEV; in riscv_early_of_processor_hartid()
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Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/sbi.h>
27 #include "copy-unaligned.h"
29 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
40 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
88 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
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/kernel/linux/linux-6.6/arch/riscv/mm/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <asm/sbi.h>
30 * Performs an icache flush for the given MM context. RISC-V has no direct
34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
47 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
60 if (mm == current->active_mm && local) { in flush_icache_mm()
64 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
87 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
89 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
129 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
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/kernel/linux/linux-6.6/include/linux/perf/
Driscv_pmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define RISCV_OP_UNSUPP (-EOPNOTSUPP)
24 #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi"
25 #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy"
/kernel/linux/linux-6.6/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
60 depends on RISCV
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Driscv_pmu_sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
24 #include <asm/sbi.h>
35 PMU_FORMAT_ATTR(event, "config:0-47");
58 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
281 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; in pmu_sbi_ctr_is_fw()
296 return -EINVAL; in riscv_pmu_get_hpm_info()
302 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) in riscv_pmu_get_hpm_info()
303 hpm_width = info->width; in riscv_pmu_get_hpm_info()
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/kernel/linux/linux-6.6/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
25 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
34 * On RISC-V systems local interrupts are masked or unmasked by writing
42 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
47 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
53 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow in riscv_intc_irq_eoi()
54 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
55 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
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/kernel/linux/linux-5.10/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
99 # VA_BITS - PAGE_SHIFT - 3
109 # set if we are running in S-mode and can use SBI calls
116 bool "MMU-based Paged Memory Management Support"
119 Select if you want MMU-based virtualised addressing space
205 source "arch/riscv/Kconfig.socs"
275 bool "Symmetric Multi-Processing"
288 int "Maximum number of CPUs (2-32)"
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/kernel/linux/linux-5.10/Documentation/riscv/
Dpmu.rst2 Supporting PMUs on RISC-V platforms
8 ------------
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
23 Counters are just free-running all the time in our case.
31 There will be an SBI to support this since the kernel cannot modify the
33 hardware-extension for M-S-U model machines to write counters directly.
44 -----------------
47 various methods according to perf's internal convention and PMU-specific
53 the minimal and already-implemented logic can be leveraged, or invent his/her
63 -----------------------
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/kernel/linux/linux-6.6/Documentation/riscv/
Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/kernel/linux/linux-5.10/drivers/tty/serial/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SERIAL_CORE) += serial_core.o
8 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
9 obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
10 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
15 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
16 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
17 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
18 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
19 obj-$(CONFIG_SERIAL_SUNSAB) += sunsab.o
[all …]
/kernel/linux/linux-6.6/drivers/tty/serial/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SERIAL_CORE) += serial_base.o
7 serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o
9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
11 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
16 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
17 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
18 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
19 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
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