Searched +full:rk3399 +full:- +full:cru (Results 1 – 25 of 137) sorted by relevance
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/ |
| D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3399-cru.txt | 1 * Rockchip RK3399 Clock and Reset Unit
3 The RK3399 clock controller generates and supplies clock to various
9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
32 clock-output-names:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/power/ |
| D | rockchip,power-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
18 Power domains contained within power-controller node are
20 Documentation/devicetree/bindings/power/power-domain.yaml.
23 "power-domains" property that is a phandle for the
28 const: power-controller
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | rockchip,rk3399-dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | rockchip,rk3399-pcie-ep.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
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| D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie
22 reg-names:
24 - const: axi-base
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3399-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 Clock and Reset Unit
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The RK3399 clock controller generates and supplies clock to various
19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
24 clock-output-names:
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/ |
| D | rockchip,vdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
19 - const: rockchip,rk3399-vdec
20 - items:
21 - enum:
22 - rockchip,rk3228-vdec
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| D | rockchip-rga.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jacob Chen <jacob-chen@iotwrt.com>
16 - Ezequiel Garcia <ezequiel@collabora.com>
21 - const: rockchip,rk3288-rga
22 - const: rockchip,rk3399-rga
23 - items:
24 - enum:
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| D | rockchip-isp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
29 interrupt-names:
31 - const: isp
32 - const: mi
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | rockchip,dwc3.txt | 4 - compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
5 - clocks: A list of phandle + clock-specifier pairs for the
6 clocks listed in clock-names
7 - clock-names: Should contain the following:
19 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
20 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
25 compatible = "rockchip,rk3399-dwc3";
26 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
27 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
28 clock-names = "ref_clk", "suspend_clk",
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | rockchip,vdec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
18 const: rockchip,rk3399-vdec
28 - description: The Video Decoder AXI interface clock
29 - description: The Video Decoder AHB interface clock
30 - description: The Video Decoded CABAC clock
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| D | rockchip-rga.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jacob Chen <jacob-chen@iotwrt.com>
16 - Ezequiel Garcia <ezequiel@collabora.com>
21 - const: rockchip,rk3288-rga
22 - const: rockchip,rk3399-rga
23 - items:
24 - const: rockchip,rk3228-rga
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | rockchip-mipi-dphy-rx0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
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| D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
12 <&cru SCLK_UPHY1_TCPDCORE>;
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
19 - rockchip,rk3568-pcie3-phy-grf
20 - rockchip,rk3568-pipe-grf
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| /kernel/linux/linux-5.10/drivers/staging/media/rkisp1/Documentation/devicetree/bindings/media/ |
| D | rockchip-isp1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
18 const: rockchip,rk3399-cif-isp
29 power-domains:
36 phy-names:
41 - description: ISP clock
42 - description: ISP AXI clock clock
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | cdn-dp-rockchip.txt | 1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/rockchip/ |
| D | cdn-dp-rockchip.txt | 1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | rockchip-dwmac.txt | 6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | rockchip-pcie-ep.txt | 4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/ |
| D | rockchip,rk3288-crypto.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/rockchip,rk3288-crypto.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3288-crypto
16 - rockchip,rk3328-crypto
17 - rockchip,rk3399-crypto
29 clock-names:
37 reset-names:
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