| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* SERDES Register */
16 /* SERDES defines */
17 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
18 #define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
40 /* Cross-timestamping defines */
|
| D | dwmac-intel.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | phy-j721e-wiz.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
[all …]
|
| D | phy-am654-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-intel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* SERDES Register */
15 /* SERDES defines */
16 #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
17 #define SERDES_RST BIT(2) /* Serdes Reset */
18 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
|
| D | dwmac-intel.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
13 int mdio_adhoc_addr; /* mdio address for serdes & etc */
41 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
46 return -ENODEV; in stmmac_pci_find_phy_addr()
48 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
49 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
51 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
52 if (func_data->func == func) in stmmac_pci_find_phy_addr()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-am654-serdes.txt | 1 TI AM654 SERDES
4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
[all …]
|
| D | qcom,qmp-usb3-dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Manu Gautam <mgautam@codeaurora.org>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7180-qmp-usb3-phy
18 - qcom,sdm845-qmp-usb3-dp-phy
19 - qcom,sdm845-qmp-usb3-phy
22 - description: Address and length of PHY's USB serdes block.
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
15 #include <linux/clk.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
16 #include <linux/clk.h>
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-pcie-msm8996.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
203 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
215 void __iomem *serdes; member
[all …]
|
| D | phy-qcom-qmp-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
[all …]
|
| D | phy-qcom-qmp-usb-legacy.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
89 /* set of registers with offsets different per-PHY */
501 u16 serdes; member
508 /* struct qmp_phy_cfg - per-PHY initialization config */
[all …]
|
| D | phy-qcom-qmp-ufs.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/ti/ |
| D | phy-j721e-wiz.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Wrapper driver for SERDES used in J721E
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
25 #include <linux/reset-controller.h>
35 /* SERDES offsets */
125 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
[all …]
|
| D | phy-am654-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe SERDES driver for AM654x SoC
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
142 /* Mid-speed initial calibration control */
145 /* High-speed initial calibration control */
148 /* Mid-speed recalibration control */
151 /* High-speed recalibration control */
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/samsung/ |
| D | phy-exynos5250-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SATA SerDes(PHY) driver
10 #include <linux/clk.h>
50 struct clk *phyclk;
66 return -EFAULT; in wait_for_reg_status()
73 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_on()
82 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_off()
94 ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_init()
97 dev_err(&sata_phy->phy->dev, "phy init failed\n"); in exynos_sata_phy_init()
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/samsung/ |
| D | phy-exynos5250-sata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SATA SerDes(PHY) driver
10 #include <linux/clk.h>
50 struct clk *phyclk;
66 return -EFAULT; in wait_for_reg_status()
73 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_on()
82 return regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_power_off()
94 ret = regmap_update_bits(sata_phy->pmureg, SATAPHY_CONTROL_OFFSET, in exynos_sata_phy_init()
97 dev_err(&sata_phy->phy->dev, "phy init failed\n"); in exynos_sata_phy_init()
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/microchip/ |
| D | sparx5_serdes.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Microchip Sparx5 Switch SerDes driver
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 …* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Swi…
18 #include <linux/clk.h>
104 u8 if_width; /* UDL if-width: 10/16/20/32/64 */
106 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
107 bool no_pwrcycle:1; /* Omit initial power-cycle */
236 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
246 bool no_pwrcycle:1; /* Omit initial power-cycle */
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-kontron-sl28-var1.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
[all …]
|
| /kernel/linux/linux-6.6/drivers/phy/marvell/ |
| D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
17 #include <linux/clk.h>
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
402 comphy_set_indirect(lane->priv, in comphy_lane_reg_set()
[all …]
|
| /kernel/linux/linux-6.6/arch/mips/boot/dts/mscc/ |
| D | ocelot.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/boot/dts/mscc/ |
| D | ocelot.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
[all …]
|
| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
83 * if yes, then offset gives index in the reg-layout
115 /* set of registers with offsets different per-PHY */
1827 /* struct qmp_phy_cfg - per-PHY initialization config */
1829 /* phy-type - PCIE/UFS/USB */
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
[all …]
|