| /kernel/linux/linux-6.6/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
37 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
40 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
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| /kernel/linux/linux-5.10/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
30 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
33 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-bus-iio-frequency-adf4371 | 3 Contact: linux-iio@vger.kernel.org
5 Stores the PLL frequency in Hz for channel Y.
6 Reading returns the actual frequency in Hz.
7 The ADF4371 has an integrated VCO with fundamendal output
8 frequency ranging from 4000000000 Hz 8000000000 Hz.
12 frequencies from 62500000 Hz to 8000000000 Hz.
17 8000000000 Hz to 16000000000 Hz.
20 16000000000 Hz to 32000000000 Hz.
23 all the other channels, since it involves changing the VCO
28 Contact: linux-iio@vger.kernel.org
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| /kernel/linux/linux-6.6/drivers/video/fbdev/kyro/ |
| D | STG4000InitDevice.c | 69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
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| /kernel/linux/linux-5.10/drivers/video/fbdev/kyro/ |
| D | STG4000InitDevice.c | 69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/ |
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wen He <wen.he_1@nxp.com>
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
41 - compatible
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| D | ti,lmk04832.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wen He <wen.he_1@nxp.com>
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
41 - compatible
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-si544.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
74 * struct clk_si544_muldiv - Multiplier/divider settings
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
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| D | clk-plldig.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
35 /* Range of the VCO frequencies, in Hz */
39 /* Range of the output frequencies, in Hz */
72 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
78 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
88 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
93 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
100 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
110 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
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| /kernel/linux/linux-6.6/drivers/clk/ |
| D | clk-si544.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
74 * struct clk_si544_muldiv - Multiplier/divider settings
79 * If ls_div_bits is non-zero, hs_div must be even
80 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
93 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
117 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
131 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
135 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
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| D | clk-plldig.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
33 /* Range of the VCO frequencies, in Hz */
37 /* Range of the output frequencies, in Hz */
70 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
76 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
86 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
91 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
98 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
108 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
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| D | clk-lmk04832.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
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| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
| D | stb6100.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
163 return -EINVAL; in stb6100_read_reg()
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| /kernel/linux/linux-6.6/drivers/media/dvb-frontends/ |
| D | stb6100.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
74 [STB6100_VCO] = "VCO",
125 .addr = state->config->tuner_address, in stb6100_read_regs()
131 rc = i2c_transfer(state->i2c, &msg, 1); in stb6100_read_regs()
134 state->config->tuner_address, rc); in stb6100_read_regs()
136 return -EREMOTEIO; in stb6100_read_regs()
141 dprintk(verbose, FE_DEBUG, 1, " Read from 0x%02x", state->config->tuner_address); in stb6100_read_regs()
153 .addr = state->config->tuner_address + reg, in stb6100_read_reg()
159 i2c_transfer(state->i2c, &msg, 1); in stb6100_read_reg()
163 return -EINVAL; in stb6100_read_reg()
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| /kernel/linux/linux-5.10/arch/powerpc/boot/ |
| D | redboot.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
|
| D | ppcboot.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
18 * include/asm-ppc/ppcboot.h
48 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
58 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
59 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
60 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
84 unsigned int bi_opbfreq; /* OB clock in Hz */
|
| D | ppcboot-hotfoot.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
11 * least-offensive solution. Please direct all flames to:
13 * Solomon Peachy <solomon@linux-wlan.com>
30 * include/asm-ppc/ppcboot.h
65 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
75 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
76 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
77 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
81 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
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| /kernel/linux/linux-6.6/arch/powerpc/boot/ |
| D | redboot.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 // include/asm-ppc/redboot.h
26 unsigned int bi_intfreq; /* Internal Freq, in Hz */
27 unsigned int bi_busfreq; /* Bus Freq, in Hz */
28 unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
29 unsigned int bi_brgfreq; /* BRG Freq, in Hz */
30 unsigned int bi_vco; /* VCO Out from PLL */
31 unsigned int bi_pci_freq; /* PCI Freq, in Hz */
|
| D | ppcboot.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
18 * include/asm-ppc/ppcboot.h
48 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
58 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
59 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
60 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
84 unsigned int bi_opbfreq; /* OB clock in Hz */
|
| D | ppcboot-hotfoot.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This interface is used for compatibility with old U-boots *ONLY*.
11 * least-offensive solution. Please direct all flames to:
13 * Solomon Peachy <solomon@linux-wlan.com>
30 * include/asm-ppc/ppcboot.h
65 unsigned long bi_vco; /* VCO Out from PLL, in MHz */
75 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
76 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
77 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
81 unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
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| /kernel/linux/linux-5.10/drivers/media/tuners/ |
| D | max2165.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
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| /kernel/linux/linux-6.6/drivers/media/tuners/ |
| D | max2165.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include "tuner-i2c.h"
38 msg.addr = priv->config->i2c_address; in max2165_write_reg()
43 ret = i2c_transfer(priv->i2c, &msg, 1); in max2165_write_reg()
49 return (ret != 1) ? -EIO : 0; in max2165_write_reg()
55 u8 dev_addr = priv->config->i2c_address; in max2165_read_reg()
64 ret = i2c_transfer(priv->i2c, msg, 2); in max2165_read_reg()
67 return -EIO; in max2165_read_reg()
104 priv->tf_ntch_low_cfg = dat[0] >> 4; in max2165_read_rom_table()
105 priv->tf_ntch_hi_cfg = dat[0] & 0x0F; in max2165_read_rom_table()
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| /kernel/linux/linux-5.10/drivers/iio/frequency/ |
| D | adf4371.c | 1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
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| /kernel/linux/linux-6.6/drivers/iio/frequency/ |
| D | adf4371.c | 1 // SPDX-License-Identifier: GPL-2.0
63 #define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
64 #define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
65 #define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
66 #define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
67 #define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
68 #define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
70 #define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
71 #define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
73 /* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
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