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/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP ZC1232 RevA";
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
26 stdout-path = "serial0:115200n8";
42 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
[all …]
Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP zc1751-xm015-dc1 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm017-dc3 RevA";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
31 stdout-path = "serial0:115200n8";
74 phy-handle = <&phy0>;
[all …]
Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "ZynqMP ZCU104 RevA";
18 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
116 phy-mode = "rgmii-id";
[all …]
Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 model = "ZynqMP zc1751-xm019-dc5 RevA";
19 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
32 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2019, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
20 model = "ZynqMP ZCU100 RevC";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZC1232
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP ZC1232 RevA";
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
27 stdout-path = "serial0:115200n8";
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
[all …]
Dzynqmp-zc1751-xm017-dc3.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/phy/phy.h>
17 model = "ZynqMP zc1751-xm017-dc3 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
[all …]
Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
117 phy-mode = "rgmii-id";
[all …]
Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
[all …]
Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU104
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
[all …]
Dzynqmp-sm-k26-revA.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 /dts-v1/;
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
[all …]
Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
[all …]
Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
14 #include "zynqmp.dtsi"
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
23 - items:
24 - enum:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
/kernel/linux/linux-5.10/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
21 #include <linux/io-64-nonatomic-lo-hi.h>
56 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
82 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
83 #define ZYNQMP_DMA_AWCACHE_OFST 8
90 #define ZYNQMP_DMA_AXCOHRNT BIT(8)
143 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
151 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
167 * struct zynqmp_dma_desc_sw - Per Transaction structure
[all …]
/kernel/linux/linux-6.6/drivers/dma/xilinx/
Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for Xilinx ZynqMP DMA Engine
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
54 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
80 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
81 #define ZYNQMP_DMA_AWCACHE_OFST 8
88 #define ZYNQMP_DMA_AXCOHRNT BIT(8)
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
149 * struct zynqmp_dma_desc_ll - Hw linked list descriptor
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/iio/adc/
Dxlnx,zynqmp-ams.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/xlnx,zynqmp-ams.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>
13 The AMS (Analog Monitoring System) includes an ADC as well as on-chip sensors
14 that can be used to sample external voltages and monitor on-die operating
27 …--------------------------------------------------------------------------------------------------…
35 …--------------------------------------------------------------------------------------------------…
37 |8 |FPD temperature measurement (REMOTE). |Temperature
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Piyush Mehta <piyush.mehta@amd.com>
14 special extensions to add functionality, is a high-performance dual-port
21 const: ceva,ahci-1v84
29 dma-coherent: true
37 power-domains:
40 ceva,p0-cominit-params:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dxlnx,zynqmp-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 ZynqMP's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,zynqmp-pinctrl
[all …]
/kernel/linux/linux-6.6/drivers/gpio/
Dgpio-zynqmp-modepin.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the ps-mode pin configuration.
16 #include <linux/firmware/xlnx-zynqmp.h>
18 /* 4-bit boot mode pins */
22 * modepin_gpio_get_value - Get the state of the specified pin of GPIO device
28 * Return: 0 if the pin is low, 1 if pin is high, -EINVAL wrong pin configured
40 /* When [0:3] corresponding bit is set, then read output bit [8:11], in modepin_gpio_get_value()
44 return !!(regval & BIT(pin + 8)); in modepin_gpio_get_value()
50 * modepin_gpio_set_value - Modify the state of the pin with specified value
72 bootpin_val |= BIT(pin + 8); in modepin_gpio_set_value()
[all …]

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