1/* 2 * Copyright (c) 2023 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16/* InsnDesc format: 17 * {mop, opndMD, properties, latency, name, format, atomicNum, validFunc(nullptr), splitFunc(nullptr), encodeType, encode} 18 */ 19 20/* AARCH64 MOVES */ 21/* MOP_xmovrr */ 22DEFINE_MOP(MOP_xmovrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},ISMOVE,kLtAlu,"mov","0,1",1,kMovReg,0x00000000) 23/* MOP_wmovrr */ 24DEFINE_MOP(MOP_wmovrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},ISMOVE,kLtAlu,"mov","0,1",1,kMovReg,0x00000000) 25/* MOP_wmovri32 */ 26DEFINE_MOP(MOP_wmovri32, {&OpndDesc::Reg32ID,&OpndDesc::Imm32},ISMOVE,kLtAlu,"mov","0,1",1,MOP_wmovri32Valid,MOP_wmovri32Split,kMovImm,0x00000000) 27/* MOP_xmovri64 */ 28DEFINE_MOP(MOP_xmovri64, {&OpndDesc::Reg64ID,&OpndDesc::Imm64},ISMOVE,kLtAlu,"mov","0,1",1,MOP_xmovri64Valid, MOP_xmovri64Split,kMovImm,0x00000000) 29/* MOP_xmovrr_uxtw -- Remove Redundant uxtw -- used in globalopt:UxtwMovPattern */ 30DEFINE_MOP(MOP_xmovrr_uxtw, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS},ISMOVE,kLtAlu,"mov","0,1",1) 31 32/* MOP_xvmovsr */ 33DEFINE_MOP(MOP_xvmovsr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32IS},ISMOVE,kLtR2f,"fmov","0,1",1,kFloatIntConversions,0x1e270000) 34/* MOP_xvmovdr */ 35DEFINE_MOP(MOP_xvmovdr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64IS},ISMOVE,kLtR2f,"fmov","0,1",1,kFloatIntConversions,0x9e670000) 36/* MOP_xvmovrs */ 37DEFINE_MOP(MOP_xvmovrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISMOVE,kLtF2r,"fmov","0,1",1,kFloatIntConversions,0x1e260000) 38/* MOP_xvmovrd */ 39DEFINE_MOP(MOP_xvmovrd, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISMOVE,kLtF2r,"fmov","0,1",1,kFloatIntConversions,0x9e660000) 40/* MOP_xvmovs */ 41DEFINE_MOP(MOP_xvmovs, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},ISMOVE,kLtFpalu,"fmov","0,1",1,kFloatDataProcessing1,0x1e204000) 42/* MOP_xvmovd */ 43DEFINE_MOP(MOP_xvmovd, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},ISMOVE,kLtFpalu,"fmov","0,1",1,kFloatDataProcessing1,0x1e604000) 44 45/* Vector SIMD mov */ 46/* MOP_xmovrv */ 47DEFINE_MOP(MOP_xvmovrv, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISMOVE,kLtF2r,"mov","0,1",1) 48 49/* MOP_xadrp */ 50DEFINE_MOP(MOP_xadrp, {&OpndDesc::Reg64ID,&OpndDesc::LiteralSrc},0,kLtShift,"adrp","0,1",1,kPCRelAddr,0x90000000) 51/* MOP_xadr */ 52DEFINE_MOP(MOP_xadri64, {&OpndDesc::Reg64ID,&OpndDesc::Imm64},0,kLtShift,"adr","0,1",1,kPCRelAddr,0x10000000) 53/* MOP_xadrpl12 */ 54 55DEFINE_MOP(MOP_xadrpl12, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Literal12Src},0,kLtAlu,"add","0,1,2",1,kAddPCRelAddr,0x91000000) 56 57/* AARCH64 Arithmetic: add */ 58/* MOP_xaddrrr */ 59DEFINE_MOP(MOP_xaddrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"add","0,1,2",1,kAddSubReg,0x8B000000) 60/* MOP_xaddsrrr */ 61DEFINE_MOP(MOP_xaddsrrr, {&OpndDesc::CCD, &OpndDesc::Reg64ID, &OpndDesc::Reg64IS, &OpndDesc::Reg64IS}, 0, kLtAlu, "adds", "1,2,3", 1) 62/* MOP_xaddrrrs */ 63DEFINE_MOP(MOP_xaddrrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAluShift,"add","0,1,2,3",1,MOP_xaddrrrsValid,kAddSubShiftReg,0x8B000000) 64/* MOP_xaddsrrrs */ 65DEFINE_MOP(MOP_xaddsrrrs, {&OpndDesc::CCD,&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAluShift,"adds","1,2,3,4",1,MOP_xaddsrrrsValid,kAddSubExtendReg,0x8b200000) 66/* MOP_xxwaddrrre */ 67DEFINE_MOP(MOP_xxwaddrrre, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAluShift,"add","0,1,2,3",1,MOP_xxwaddrrreValid,kAddSubExtendReg,0x8B200000) 68/* MOP_xaddrri24 */ 69DEFINE_MOP(MOP_xaddrri24, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtShift,"add","0,1,2,3",1,MOP_xaddrri24Valid,MOP_xaddrri24Split,kAddSubShiftImm,0x91000000) 70/* MOP_xaddrri12 */ 71DEFINE_MOP(MOP_xaddrri12, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12},0,kLtAlu,"add","0,1,2",1,MOP_xaddrri12Valid,MOP_xaddrri12Split,kAddSubImm,0x91000000) 72/* MOP_xaddsrri12 */ 73DEFINE_MOP(MOP_xaddsrri12, {&OpndDesc::CCD, &OpndDesc::Reg64ID, &OpndDesc::Reg64IS, &OpndDesc::Imm12}, 0, kLtAlu, "adds", "1,2,3", 1, MOP_xaddsrri12Valid,MOP_xaddsrri12Split) 74/* MOP_waddrrr */ 75DEFINE_MOP(MOP_waddrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"add","0,1,2",1,kAddSubReg,0xb000000) 76/* MOP_waddrrrs */ 77DEFINE_MOP(MOP_waddrrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAluShift,"add","0,1,2,3",1,MOP_waddrrrsValid, kAddSubShiftReg,0xb000000) 78/* MOP_waddsrrr */ 79DEFINE_MOP(MOP_waddsrrr, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"adds","1,2,3",1, kAddSubReg, 0x2b000000) 80/* MOP_waddsrrrs */ 81DEFINE_MOP(MOP_waddsrrrs, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAluShift,"adds","1,2,3,4",1,MOP_waddsrrrsValid,kAddSubExtendReg, 0xb200000) 82/* MOP_xxwaddrrre */ 83DEFINE_MOP(MOP_wwwaddrrre, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAluShift,"add","0,1,2,3",1,MOP_wwwaddrrreValid,kAddSubExtendReg, 0xB200000) 84/* MOP_waddrri24 */ 85DEFINE_MOP(MOP_waddrri24, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtAluShift,"add","0,1,2,3",1,MOP_waddrri24Valid,MOP_waddrri24Split,kAddSubShiftImm,0x11000000) 86/* MOP_waddrri12 */ 87DEFINE_MOP(MOP_waddrri12, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"add","0,1,2",1,MOP_waddrri12Valid,MOP_waddrri12Split,kAddSubImm,0x11000000) 88/* MOP_waddsrri12 */ 89DEFINE_MOP(MOP_waddsrri12, {&OpndDesc::CCD, &OpndDesc::Reg32ID, &OpndDesc::Reg32IS, &OpndDesc::Imm12}, 0, kLtAlu, "adds", "1,2,3", 1,MOP_waddsrri12Valid,MOP_waddsrri12Split) 90/* MOP_dadd */ 91DEFINE_MOP(MOP_dadd, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fadd","0,1,2",1,kFloatDataProcessing2,0x1e602800) 92/* MOP_sadd */ 93DEFINE_MOP(MOP_sadd, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fadd","0,1,2",1,kFloatDataProcessing2,0x1e202800) 94 95/* AARCH64 Arithmetic: sub */ 96/* MOP_xsubrrr */ 97DEFINE_MOP(MOP_xsubrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"sub","0,1,2",1,kAddSubReg,0xcb000000) 98/* MOP_xsubsrrr */ 99DEFINE_MOP(MOP_xsubsrrr, {&OpndDesc::CCD, &OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"subs","1,2,3",1, kAddSubReg, 0xeb000000) 100/* MOP_xsubrrrs */ 101DEFINE_MOP(MOP_xsubrrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAluShift,"sub","0,1,2,3",1,MOP_xsubrrrsValid,kAddSubShiftReg, 0xcb000000) 102/* MOP_xxwsubrrre */ 103DEFINE_MOP(MOP_xxwsubrrre, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAluShift,"sub","0,1,2,3",1, kAddSubExtendReg, 0xcb200000) 104/* MOP_xsubsrrrs */ 105DEFINE_MOP(MOP_xsubsrrrs, {&OpndDesc::CCD, &OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAluShift,"subs","1,2,3,4",1,MOP_xsubsrrrsValid,kAddSubShiftReg, 0xeb000000) 106/* MOP_xsubrri24 */ 107DEFINE_MOP(MOP_xsubrri24, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtAluShift,"sub","0,1,2,3",1,MOP_xsubrri24Valid, MOP_xsubrri24Split,kAddSubShiftImm,0xd1000000) 108/* MOP_xsubsrri24 */ 109DEFINE_MOP(MOP_xsubsrri24, {&OpndDesc::CCD, &OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtAluShift,"subs","1,2,3,4",1,MOP_xsubsrri24Valid,kAddSubShiftImm, 0xf1000000) 110/* MOP_xsubrri12 */ 111DEFINE_MOP(MOP_xsubrri12, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12},0,kLtAlu,"sub","0,1,2",1,MOP_xsubrri12Valid,MOP_xsubrri12Split,kAddSubImm,0xd1000000) 112/* MOP_xsubsrri12 */ 113DEFINE_MOP(MOP_xsubsrri12, {&OpndDesc::CCD, &OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm12},0,kLtAlu,"subs","1,2,3",1,MOP_xsubsrri12Valid,MOP_xsubsrri12Split, kAddSubImm, 0xf1000000) 114/* MOP_wsubrrr */ 115DEFINE_MOP(MOP_wsubrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"sub","0,1,2",1,kAddSubReg,0x4b000000) 116/* MOP_wsubsrrr */ 117DEFINE_MOP(MOP_wsubsrrr, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"subs","1,2,3",1, kAddSubReg, 0x6b000000) 118/* MOP_wsubrrrs */ 119DEFINE_MOP(MOP_wsubrrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAluShift,"sub","0,1,2,3",1,MOP_wsubrrrsValid,kAddSubShiftReg, 0x4b000000) 120/* MOP_wwwsubrrre */ 121DEFINE_MOP(MOP_wwwsubrrre, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAluShift,"sub","0,1,2,3",1, kAddSubExtendReg, 0x4b200000) 122/* MOP_wsubsrrrs */ 123DEFINE_MOP(MOP_wsubsrrrs, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAluShift,"subs","1,2,3,4",1,MOP_wsubsrrrsValid,kAddSubShiftReg, 0x6b000000) 124/* MOP_wsubrri24 */ 125DEFINE_MOP(MOP_wsubrri24, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtAluShift,"sub","0,1,2,3",1,MOP_wsubrri24Valid,MOP_wsubrri24Split,kAddSubShiftImm,0x51000000) 126/* MOP_wsubsrri24 */ 127DEFINE_MOP(MOP_wsubsrri24, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12,&OpndDesc::Lsl12},0,kLtAluShift,"subs","1,2,3,4",1,MOP_wsubsrri24Valid,kAddSubShiftImm, 0x71000000) 128/* MOP_wsubrri12 */ 129DEFINE_MOP(MOP_wsubrri12, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"sub","0,1,2",1,MOP_wsubrri12Valid,MOP_wsubrri12Split,kAddSubImm,0x51000000) 130/* MOP_wsubsrri12 */ 131DEFINE_MOP(MOP_wsubsrri12, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"subs","1,2,3",1,MOP_wsubsrri12Valid,MOP_wsubsrri12Split,kAddSubImm, 0x71000000) 132/* MOP_dsub */ 133DEFINE_MOP(MOP_dsub, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fsub","0,1,2",1,kFloatDataProcessing2,0x1e603800) 134/* MOP_ssub */ 135DEFINE_MOP(MOP_ssub, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fsub","0,1,2",1,kFloatDataProcessing2,0x1e203800) 136 137/* AARCH64 Arithmetic: multiply */ 138/* MOP_Tbxmulrrr */ 139DEFINE_MOP(MOP_xmulrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtMul,"mul","0,1,2",1,kDataProcess3Src,0x9b007c00) 140/* MOP_wmulrrr */ 141DEFINE_MOP(MOP_wmulrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtMul,"mul","0,1,2",1,kDataProcess3Src,0x1b007c00) 142/* MOP_Tbxvmuls */ 143DEFINE_MOP(MOP_xvmuls, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpmul,"fmul","0,1,2",1,kFloatDataProcessing2,0x1e200800) 144/* MOP_Tbxvmuld */ 145DEFINE_MOP(MOP_xvmuld, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpmul,"fmul","0,1,2",1,kFloatDataProcessing2,0x1e600800) 146/*MOP_xsmullrrr */ 147DEFINE_MOP(MOP_xsmullrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtMul,"smull","0,1,2",1,kDataProcess3Src,0x9b207c00) 148 149/* AARCH64 Arithmetic: multiply first then add */ 150/* MOP_xmaddrrrr */ 151DEFINE_MOP(MOP_xmaddrrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtMul,"madd","0,1,2,3",1, kDataProcess3Src, 0x1b000000) 152/* MOP_wmaddrrrr */ 153DEFINE_MOP(MOP_wmaddrrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtMul,"madd","0,1,2,3",1, kDataProcess3Src, 0x9b000000) 154 155/* AARCH64 leading zeros, reverse bits (for trailing zeros) */ 156/* MOP_wclz */ 157DEFINE_MOP(MOP_wclz, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"clz","0,1", 1, kDataProcess1Src, 0x5ac01000) 158/* MOP_xclz */ 159DEFINE_MOP(MOP_xclz, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"clz","0,1", 1, kDataProcess1Src, 0xdac01000) 160/* MOP_wcls */ 161DEFINE_MOP(MOP_wcls, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"cls","0,1", 1, kDataProcess1Src, 0x5ac01400) 162/* MOP_xcls */ 163DEFINE_MOP(MOP_xcls, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"cls","0,1", 1, kDataProcess1Src, 0xdac01400) 164/* MOP_wrbit */ 165DEFINE_MOP(MOP_wrbit, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"rbit","0,1", 1, kDataProcess1Src, 0x5ac00000) 166/* MOP_xrbit */ 167DEFINE_MOP(MOP_xrbit, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"rbit","0,1", 1, kDataProcess1Src, 0xdac00000) 168/* MOP_xrevrr */ 169DEFINE_MOP(MOP_xrevrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"rev","0,1",1, kDataProcess1Src, 0xdac00c00) 170/* MOP_wrevrr */ 171DEFINE_MOP(MOP_wrevrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"rev","0,1",1, kDataProcess1Src, 0x5ac00800) 172/* MOP_xrevrr */ 173DEFINE_MOP(MOP_wrevrr16, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"rev16","0,1",1, kDataProcess1Src, 0x5ac00400) 174DEFINE_MOP(MOP_xrevrr16, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"rev16","0,1",1, kDataProcess1Src, 0xdac00400) 175 176/* AARCH64 Conversions */ 177/* MOP_xsxtb32 */ 178DEFINE_MOP(MOP_xsxtb32, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"sxtb","0,1",1,kBitfield,0x13001c00) 179/* MOP_xsxtb64 */ 180DEFINE_MOP(MOP_xsxtb64, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"sxtb","0,1",1,kBitfield,0x93401c00) 181/* MOP_xsxth32 */ 182DEFINE_MOP(MOP_xsxth32, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"sxth","0,1",1,kBitfield,0x13003c00) 183/* MOP_xsxth64 */ 184DEFINE_MOP(MOP_xsxth64, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"sxth","0,1",1,kBitfield,0x93403c00) 185/* MOP_xsxtw64 */ 186DEFINE_MOP(MOP_xsxtw64, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"sxtw","0,1",1,kBitfield,0x93407c00) 187 188/* MOP_xuxtb32 */ 189DEFINE_MOP(MOP_xuxtb32, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"uxtb","0,1",1,kBitfield,0x53001c00) 190/* MOP_xuxth32 */ 191DEFINE_MOP(MOP_xuxth32, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"uxth","0,1",1,kBitfield,0x53003c00) 192/* MOP_xuxtw64 Same as mov w0,w0 */ 193DEFINE_MOP(MOP_xuxtw64, {&OpndDesc::Reg64ID,&OpndDesc::Reg32IS},ISCONVERSION,kLtAluShift,"uxtw","0,1",1,kBitfield,0xd3407c00) 194 195/* MOP_xvcvtfd */ 196DEFINE_MOP(MOP_xvcvtfd, {&OpndDesc::Reg32FD,&OpndDesc::Reg64FS},ISCONVERSION,kLtFpalu,"fcvt","0,1",1,kFloatDataProcessing1,0x1e624000) 197/* MOP_xvcvtdf */ 198DEFINE_MOP(MOP_xvcvtdf, {&OpndDesc::Reg64FD,&OpndDesc::Reg32FS},ISCONVERSION,kLtFpalu,"fcvt","0,1",1,kFloatDataProcessing1,0x1e22c000) 199 200/* MOP_vcvtrf fcvtzs w,s */ 201DEFINE_MOP(MOP_vcvtrf, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtzs","0,1",1,kFloatIntConversions,0x1e380000) 202/* MOP_xvcvtrf fcvtzs x,s */ 203DEFINE_MOP(MOP_xvcvtrf, {&OpndDesc::Reg64ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtzs","0,1",1,kFloatIntConversions,0x9e380000) 204/* MOP_vcvturf fcvtzu w,s */ 205DEFINE_MOP(MOP_vcvturf, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtzu","0,1",1,kFloatIntConversions,0x1e390000) 206/* MOP_xvcvturf fcvtzu x,s */ 207DEFINE_MOP(MOP_xvcvturf, {&OpndDesc::Reg64ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtzu","0,1",1,kFloatIntConversions,0x9e390000) 208 209/* MOP_vcvtas fcvtas w,s (for round) */ 210DEFINE_MOP(MOP_vcvtas, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtas","0,1",1,kFloatIntConversions,0x1e240000) 211/* MOP_xvcvtas fcvtas x,s */ 212DEFINE_MOP(MOP_xvcvtas, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtas","0,1",1,kFloatIntConversions,0x9e640000) 213/* MOP_vcvtms fcvtms w,s (for floor) */ 214DEFINE_MOP(MOP_vcvtms, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtms","0,1",1,kFloatIntConversions,0x1e300000) 215/* MOP_xvcvtms fcvtms x,s */ 216DEFINE_MOP(MOP_xvcvtms, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtms","0,1",1,kFloatIntConversions,0x9e700000) 217/* MOP_vcvtps fcvtps w,s (for ceil) */ 218DEFINE_MOP(MOP_vcvtps, {&OpndDesc::Reg32ID,&OpndDesc::Reg32FS},ISCONVERSION,kLtF2rCvt,"fcvtps","0,1",1,kFloatIntConversions,0x1e280000) 219/* MOP_xvcvtps fcvtps x,d */ 220DEFINE_MOP(MOP_xvcvtps, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtps","0,1",1,kFloatIntConversions,0x9e680000) 221 222/* MOP_vcvtrd fcvtzs w,d */ 223DEFINE_MOP(MOP_vcvtrd, {&OpndDesc::Reg32ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtzs","0,1",1,kFloatIntConversions,0x1e780000) 224/* MOP_xvcvtrd fcvtzs x,d */ 225DEFINE_MOP(MOP_xvcvtrd, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtzs","0,1",1,kFloatIntConversions,0x9e780000) 226/* MOP_vcvturd fcvtzu w,d */ 227DEFINE_MOP(MOP_vcvturd, {&OpndDesc::Reg32ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtzu","0,1",1,kFloatIntConversions,0x1e790000) 228/* MOP_xvcvturd fcvtzu x,d */ 229DEFINE_MOP(MOP_xvcvturd, {&OpndDesc::Reg64ID,&OpndDesc::Reg64FS},ISCONVERSION,kLtF2rCvt,"fcvtzu","0,1",1,kFloatIntConversions,0x9e790000) 230 231/* MOP_vcvtfr scvtf s,w */ 232DEFINE_MOP(MOP_vcvtfr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32IS},ISCONVERSION,kLtR2fCvt,"scvtf","0,1",1,kFloatIntConversions,0x1e220000) 233/* MOP_xvcvtfr scvtf s,x */ 234DEFINE_MOP(MOP_xvcvtfr, {&OpndDesc::Reg32FD,&OpndDesc::Reg64IS},ISCONVERSION,kLtR2fCvt,"scvtf","0,1",1,kFloatIntConversions,0x9e220000) 235/* MOP_vcvtufr ucvtf s,w */ 236DEFINE_MOP(MOP_vcvtufr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32IS},ISCONVERSION,kLtR2fCvt,"ucvtf","0,1",1,kFloatIntConversions,0x1e230000) 237/* MOP_xvcvtufr ucvtf s,x */ 238DEFINE_MOP(MOP_xvcvtufr, {&OpndDesc::Reg32FD,&OpndDesc::Reg64IS},ISCONVERSION,kLtR2fCvt,"ucvtf","0,1",1,kFloatIntConversions,0x9e230000) 239 240/* MOP_vcvtdr scvtf d,w */ 241DEFINE_MOP(MOP_vcvtdr, {&OpndDesc::Reg64FD,&OpndDesc::Reg32IS},ISCONVERSION,kLtR2fCvt,"scvtf","0,1",1,kFloatIntConversions,0x1e620000) 242/* MOP_xvcvtdr scvtf d,x */ 243DEFINE_MOP(MOP_xvcvtdr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64IS},ISCONVERSION,kLtR2fCvt,"scvtf","0,1",1,kFloatIntConversions,0x9e620000) 244/* MOP_vcvtudr ucvtf d,w */ 245DEFINE_MOP(MOP_vcvtudr, {&OpndDesc::Reg64FD,&OpndDesc::Reg32IS},ISCONVERSION,kLtR2fCvt,"ucvtf","0,1",1,kFloatIntConversions,0x1e630000) 246/* MOP_xvcvtudr ucvtf d,x */ 247DEFINE_MOP(MOP_xvcvtudr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64IS},ISCONVERSION,kLtR2fCvt,"ucvtf","0,1",1,kFloatIntConversions,0x9e630000) 248 249/* MOP_xcsel */ 250DEFINE_MOP(MOP_wcselrrrc, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csel","0,1,2,3",1,kConditionalSelect,0x1a800000) 251DEFINE_MOP(MOP_xcselrrrc, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csel","0,1,2,3",1,kConditionalSelect,0x9A800000) 252 253/* MOP_xcset -- all conditions minus AL & NV */ 254DEFINE_MOP(MOP_wcsetrc, {&OpndDesc::Reg32ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cset","0,1",1,kConditionalSelect,0x1a9f07e0) 255DEFINE_MOP(MOP_xcsetrc, {&OpndDesc::Reg64ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cset","0,1",1,kConditionalSelect,0x9a9f07e0) 256 257/* MOP_xcsetm -- all conditions minus AL & NV */ 258DEFINE_MOP(MOP_wcsetmrc, {&OpndDesc::Reg32ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csetm","0,1",1) 259DEFINE_MOP(MOP_xcsetmrc, {&OpndDesc::Reg64ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csetm","0,1",1) 260 261DEFINE_MOP(MOP_wcincrc, {&OpndDesc::Reg32ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cinc","0,1,2",1) 262DEFINE_MOP(MOP_xcincrc, {&OpndDesc::Reg64ID,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cinc","0,1,2",1) 263 264/* MOP_xcsinc */ 265DEFINE_MOP(MOP_wcsincrrrc, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csinc","0,1,2,3",1,kConditionalSelect,0x1a800400) 266DEFINE_MOP(MOP_xcsincrrrc, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csinc","0,1,2,3",1,kConditionalSelect,0x9a800400) 267 268/* MOP_xcsinv */ 269DEFINE_MOP(MOP_wcsinvrrrc, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csinv","0,1,2,3",1,kConditionalSelect,0x5a800000) 270DEFINE_MOP(MOP_xcsinvrrrc, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csinv","0,1,2,3",1,kConditionalSelect,0xda800000) 271 272/* MOP_xandrrr */ 273DEFINE_MOP(MOP_xandrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"and","0,1,2",1,kLogicalReg,0x8a000000) 274/* MOP_xandrrrs */ 275DEFINE_MOP(MOP_xandrrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAluShift,"and","0,1,2,3",1,MOP_xandrrrsValid,kLogicalReg,0x8a000000) 276/* MOP_xandrri13 */ 277DEFINE_MOP(MOP_xandrri13, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm13},0,kLtAlu,"and","0,1,2",1,MOP_xandrri13Valid,kLogicalImm,0x92000000) 278/* MOP_wandrrr */ 279DEFINE_MOP(MOP_wandrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"and","0,1,2",1,kLogicalReg,0xa000000) 280/* MOP_wandrrrs */ 281DEFINE_MOP(MOP_wandrrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAluShift,"and","0,1,2,3",1,MOP_wandrrrsValid,kLogicalReg,0xa000000) 282/* MOP_wandrri12 */ 283DEFINE_MOP(MOP_wandrri12, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"and","0,1,2",1,MOP_wandrri12Valid,kLogicalImm,0x12000000) 284 285/* MOP_xbicrrr */ 286DEFINE_MOP(MOP_xbicrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"bic","0,1,2",1, kLogicalReg, 0x8a200000) 287/* MOP_wbicrrr */ 288DEFINE_MOP(MOP_wbicrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"bic","0,1,2",1, kLogicalReg, 0xa200000) 289 290/* MOP_xiorrrr */ 291DEFINE_MOP(MOP_xiorrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"orr","0,1,2",1,kLogicalReg,0xaa000000) 292/* MOP_xiorrrrs */ 293DEFINE_MOP(MOP_xiorrrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAlu,"orr","0,1,2,3",1,MOP_xiorrrrsValid,kLogicalReg,0xaa000000) 294/* MOP_xiorrri13 */ 295DEFINE_MOP(MOP_xiorrri13, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm13},0,kLtAlu,"orr","0,1,2",1,MOP_xiorrri13Valid,kLogicalImm,0xb2000000) 296/* MOP_wiorrrr */ 297DEFINE_MOP(MOP_wiorrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"orr","0,1,2",1,kLogicalReg,0x2a000000) 298/* MOP_wiorrrrs */ 299DEFINE_MOP(MOP_wiorrrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAlu,"orr","0,1,2,3",1,MOP_wiorrrrsValid,kLogicalReg,0x2a000000) 300/* MOP_wiorrri12 */ 301DEFINE_MOP(MOP_wiorrri12, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"orr","0,1,2",1,MOP_wiorrri12Valid,kLogicalImm,0x32000000) 302 303/* MOP_xeorrrr */ 304DEFINE_MOP(MOP_xeorrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"eor","0,1,2",1,kLogicalReg,0xca000000) 305/* MOP_xeorrrrs */ 306DEFINE_MOP(MOP_xeorrrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAlu,"eor","0,1,2,3",1,MOP_xeorrrrsValid,kLogicalReg,0xca000000) 307/* MOP_xeorrri13 */ 308DEFINE_MOP(MOP_xeorrri13, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm13},0,kLtAlu,"eor","0,1,2",1,MOP_xeorrri13Valid,kLogicalImm,0xd2000000) 309/* MOP_weorrrr */ 310DEFINE_MOP(MOP_weorrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"eor","0,1,2",1,kLogicalReg,0x4a000000) 311/* MOP_weorrrrs */ 312DEFINE_MOP(MOP_weorrrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAlu,"eor","0,1,2,3",1,MOP_weorrrrsValid,kLogicalReg,0x4a000000) 313/* MOP_weorrri12 */ 314DEFINE_MOP(MOP_weorrri12, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"eor","0,1,2",1,MOP_weorrri12Valid,kLogicalImm,0x52000000) 315 316/* MOP_xnotrr */ 317DEFINE_MOP(MOP_xnotrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"mvn","0,1",1,kLogicalReg,0xaa2003e0) 318/* MOP_wnotrr */ 319DEFINE_MOP(MOP_wnotrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"mvn","0,1",1,kLogicalReg,0x2a2003e0) 320/* MOP_vnotui */ 321DEFINE_MOP(MOP_vnotui, {&OpndDesc::Reg64VD,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"mvni","0,1",1) 322/* MOP_vnotvi */ 323DEFINE_MOP(MOP_vnotvi, {&OpndDesc::Reg128VD,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"mvni","0,1",1) 324 325/* MOP_wfmaxrrr */ 326DEFINE_MOP(MOP_wfmaxrrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fmax","0,1,2",1,kFloatDataProcessing2,0x1e204800) 327/* MOP_xfmaxrrr */ 328DEFINE_MOP(MOP_xfmaxrrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fmax","0,1,2",1,kFloatDataProcessing2,0x1e604800) 329/* MOP_wfminrrr */ 330DEFINE_MOP(MOP_wfminrrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fmin","0,1,2",1,kFloatDataProcessing2,0x1e205800) 331/* MOP_xfminrrr */ 332DEFINE_MOP(MOP_xfminrrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fmin","0,1,2",1,kFloatDataProcessing2,0x1e605800) 333 334/* MOP_wsdivrrr */ 335DEFINE_MOP(MOP_wsdivrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},CANTHROW,kLtDiv,"sdiv","0,1,2",1,kDataProcess2Src,0x1ac00c00) 336/* MOP_xsdivrrr */ 337DEFINE_MOP(MOP_xsdivrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},CANTHROW,kLtDiv,"sdiv","0,1,2",1,kDataProcess2Src,0x9ac00c00) 338/* MOP_wudivrrr */ 339DEFINE_MOP(MOP_wudivrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},CANTHROW,kLtDiv,"udiv","0,1,2",1,kDataProcess2Src,0x1ac00800) 340/* MOP_xudivrrr */ 341DEFINE_MOP(MOP_xudivrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},CANTHROW,kLtDiv,"udiv","0,1,2",1,kDataProcess2Src,0x9ac00800) 342 343/* MOP_wmsubrrrr */ 344DEFINE_MOP(MOP_wmsubrrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtMul,"msub","0,1,2,3",1,kDataProcess3Src,0x1b008000) 345/* MOP_xmsubrrrr */ 346DEFINE_MOP(MOP_xmsubrrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtMul,"msub","0,1,2,3",1,kDataProcess3Src,0x9b008000) 347 348/* MOP_wmnegrrr */ 349DEFINE_MOP(MOP_wmnegrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtMul,"mneg","0,1,2",1, kDataProcess3Src, 0x1b00fc00) 350/* MOP_xmnegrrr */ 351DEFINE_MOP(MOP_xmnegrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtMul,"mneg","0,1,2",1, kDataProcess3Src, 0x9b00fc00) 352 353/* MOP_wubfxrri5i5 */ 354DEFINE_MOP(MOP_wubfxrri5i5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm5,&OpndDesc::Imm5},0,kLtAluShift,"ubfx","0,1,2,3",1,MOP_wubfxrri5i5Valid,kBitfield,0x53000000) 355/* MOP_xubfxrri6i6 */ 356DEFINE_MOP(MOP_xubfxrri6i6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6,&OpndDesc::Imm6},0,kLtAluShift,"ubfx","0,1,2,3",1,MOP_xubfxrri6i6Valid,kBitfield,0xd3400000) 357 358/* MOP_wsbfxrri5i5 -- Signed Bitfield Extract */ 359DEFINE_MOP(MOP_wsbfxrri5i5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm5,&OpndDesc::Imm5},0,kLtAluShift,"sbfx","0,1,2,3",1,MOP_wsbfxrri5i5Valid,kBitfield,0x13000000) 360/* MOP_xsbfxrri6i6 */ 361DEFINE_MOP(MOP_xsbfxrri6i6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6,&OpndDesc::Imm6},0,kLtAluShift,"sbfx","0,1,2,3",1,MOP_xsbfxrri6i6Valid,kBitfield,0x93400000) 362 363/* MOP_wubfizrri5i5 -- Unsigned Bitfield Insert in Zero */ 364DEFINE_MOP(MOP_wubfizrri5i5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm5,&OpndDesc::Imm5},0,kLtAluShift,"ubfiz","0,1,2,3",1,MOP_wubfizrri5i5Valid,kBitfield,0x53000000) 365/* MOP_xubfizrri6i6 */ 366DEFINE_MOP(MOP_xubfizrri6i6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6,&OpndDesc::Imm6},0,kLtAluShift,"ubfiz","0,1,2,3",1,MOP_xubfizrri6i6Valid,kBitfield,0xd3400000) 367 368/* MOP_xsbfizrri6i6 Signed Bitfield Insert in Zero */ 369DEFINE_MOP(MOP_xsbfizrri6i6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6,&OpndDesc::Imm6},0,kLtAluShift,"sbfiz","0,1,2,3",1,MOP_xsbfizrri6i6Valid,kBitfield, 0x13000000) 370 371/* MOP_wbfirri5i5 -- Bitfield Insert */ 372DEFINE_MOP(MOP_wbfirri5i5, {&OpndDesc::Reg32IDS,&OpndDesc::Reg32IS,&OpndDesc::Imm5,&OpndDesc::Imm5},ISMOVE,kLtAluShift,"bfi","0,1,2,3",1,MOP_wbfirri5i5Valid,kBitfield,0x33000000) 373/* MOP_xbfirri6i6 */ 374DEFINE_MOP(MOP_xbfirri6i6, {&OpndDesc::Reg64IDS,&OpndDesc::Reg64IS,&OpndDesc::Imm6,&OpndDesc::Imm6},ISMOVE,kLtAluShift,"bfi","0,1,2,3",1,MOP_xbfirri6i6Valid,kBitfield,0xb3400000) 375 376/* MOP_xlslrri6,--- Logical Shift Left */ 377DEFINE_MOP(MOP_xlslrri6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6},0,kLtAluShift,"lsl","0,1,2",1,MOP_xlslrri6Valid,kBitfield,0xd3400000) 378/* MOP_wlslrri5 */ 379DEFINE_MOP(MOP_wlslrri5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm8},0,kLtAluShift,"lsl","0,1,2",1,MOP_wlslrri5Valid,kBitfield,0x53000000) 380/* MOP_xasrrri6, */ 381DEFINE_MOP(MOP_xasrrri6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6},0,kLtAluShift,"asr","0,1,2",1,MOP_xasrrri6Valid,kBitfield,0x9340fc00) 382/* MOP_wasrrri5 */ 383DEFINE_MOP(MOP_wasrrri5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm8},0,kLtAluShift,"asr","0,1,2",1,MOP_wasrrri5Valid,kBitfield,0x13007c00) 384/* MOP_xlsrrri6, */ 385DEFINE_MOP(MOP_xlsrrri6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Imm6},0,kLtAluShift,"lsr","0,1,2",1,MOP_xlsrrri6Valid,kBitfield,0xd340fc00) 386/* MOP_wlsrrri5 */ 387DEFINE_MOP(MOP_wlsrrri5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Imm8},0,kLtAluShift,"lsr","0,1,2",1,MOP_wlsrrri5Valid,kBitfield,0x53007c00) 388/* MOP_xlslrrr, */ 389DEFINE_MOP(MOP_xlslrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAluShiftReg,"lsl","0,1,2",1,kDataProcess2Src,0x9ac02000) 390/* MOP_wlslrrr */ 391DEFINE_MOP(MOP_wlslrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAluShiftReg,"lsl","0,1,2",1,kDataProcess2Src,0x1ac02000) 392/* MOP_xasrrrr, */ 393DEFINE_MOP(MOP_xasrrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAluShiftReg,"asr","0,1,2",1,kDataProcess2Src,0x9ac02800) 394/* MOP_wasrrrr */ 395DEFINE_MOP(MOP_wasrrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAluShiftReg,"asr","0,1,2",1,kDataProcess2Src,0x1ac02800) 396/* MOP_xlsrrrr, */ 397DEFINE_MOP(MOP_xlsrrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAluShiftReg,"lsr","0,1,2",1,kDataProcess2Src,0x9ac02400) 398/* MOP_wlsrrrr */ 399DEFINE_MOP(MOP_wlsrrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAluShiftReg,"lsr","0,1,2",1,kDataProcess2Src,0x1ac02400) 400 401/* MOP_xrorrrr */ 402DEFINE_MOP(MOP_xrorrrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAluShiftReg,"ror","0,1,2",1, kDataProcess2Src, 0x9ac02c00) 403/* MOP_wrorrrr */ 404DEFINE_MOP(MOP_wrorrrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAluShiftReg,"ror","0,1,2",1, kDataProcess2Src, 0x1ac02c00) 405/* MOP_wtstri32 */ 406DEFINE_MOP(MOP_wtstri32, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Imm32},0,kLtAlu,"tst","1,2",1,MOP_wtstri32Valid,kLogicalImm, 0x7200001f) 407/* MOP_xtstri64 */ 408DEFINE_MOP(MOP_xtstri64, {&OpndDesc::CCD,&OpndDesc::Reg64ID,&OpndDesc::Imm64},0,kLtAlu,"tst","1,2",1,MOP_xtstri64Valid,kLogicalImm, 0xf200001f) 409/* MOP_wtstrr */ 410DEFINE_MOP(MOP_wtstrr, {&OpndDesc::CCD,&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"tst","1,2",1, kLogicalReg, 0x6a00001f) 411/* MOP_xtstrr */ 412DEFINE_MOP(MOP_xtstrr, {&OpndDesc::CCD,&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"tst","1,2",1, kLogicalReg, 0xea00001f) 413/* MOP_wextrrrri5 -- Extracts a register from a pair of registers */ 414DEFINE_MOP(MOP_wextrrrri5, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Imm5},0,kLtAluShift,"extr","0,1,2,3",1,MOP_wextrrrri5Valid,kExtract, 0x13800000) 415/* MOP_xextrrrri6 */ 416DEFINE_MOP(MOP_xextrrrri6, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Imm6},0,kLtAluShift,"extr","0,1,2,3",1,MOP_xextrrrri6Valid,kExtract, 0x93c00000) 417 418/* MOP_wsfmovri imm8->s */ 419DEFINE_MOP(MOP_wsfmovri, {&OpndDesc::Reg32FD,&OpndDesc::Imm8},ISMOVE,kLtFconst,"fmov","0,1",1,kFloatImm,0x1e201000) 420/* MOP_xdfmovri imm8->d */ 421DEFINE_MOP(MOP_xdfmovri, {&OpndDesc::Reg64FD,&OpndDesc::Imm8},ISMOVE,kLtFconst,"fmov","0,1",1,kFloatImm,0x1e601000) 422 423/* MOP_xcsneg -- Conditional Select Negation */ 424DEFINE_MOP(MOP_wcsnegrrrc, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csneg","0,1,2,3",1,kConditionalSelect,0x5a800400) 425DEFINE_MOP(MOP_xcsnegrrrc, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"csneg","0,1,2,3",1,kConditionalSelect,0xda800400) 426DEFINE_MOP(MOP_wcnegrrrc, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cneg","0,1,2",1, kConditionalSelect, 0x5a800400) 427DEFINE_MOP(MOP_xcnegrrrc, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtAlu,"cneg","0,1,2",1, kConditionalSelect, 0xda800400) 428 429/* MOP_sabsrr */ 430DEFINE_MOP(MOP_sabsrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},0,kLtFpalu,"fabs","0,1",1,kFloatDataProcessing1,0x1e20c000) 431/* MOP_dabsrr */ 432DEFINE_MOP(MOP_dabsrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},0,kLtFpalu,"fabs","0,1",1,kFloatDataProcessing1,0x1e60c000) 433 434/* MOP_winegrr */ 435DEFINE_MOP(MOP_winegrr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS},0,kLtAlu,"neg","0,1",1,kAddSubReg,0x4b0003e0) 436/* MOP_winegrre */ 437DEFINE_MOP(MOP_winegrrs, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAlu,"neg","0,1,2",1,MOP_winegrrsValid,kAddSubShiftReg, 0x4b0003e0) 438/* neg MOP_xinegrr */ 439DEFINE_MOP(MOP_xinegrr, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS},0,kLtAlu,"neg","0,1",1,kAddSubReg,0xcb0003e0) 440/* neg MOP_xinegrrs */ 441DEFINE_MOP(MOP_xinegrrs, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAlu,"neg","0,1,2",1,MOP_xinegrrsValid,kAddSubShiftReg, 0xcb0003e0) 442/* neg f32 */ 443DEFINE_MOP(MOP_wfnegrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},0,kLtFpalu,"fneg","0,1",1,kFloatDataProcessing1,0x1e214000) 444/* neg f64 */ 445DEFINE_MOP(MOP_xfnegrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},0,kLtFpalu,"fneg","0,1",1,kFloatDataProcessing1,0x1e614000) 446 447/* MOP_sdivrrr */ 448DEFINE_MOP(MOP_sdivrrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"fdiv","0,1,2",1,kFloatDataProcessing2,0x1e201800) 449/* MOP_ddivrrr */ 450DEFINE_MOP(MOP_ddivrrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivD,"fdiv","0,1,2",1,kFloatDataProcessing2,0x1e601800) 451 452/* MOP_smadd */ 453DEFINE_MOP(MOP_smadd, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},CANTHROW,kLtFpmac,"fmadd","0,1,2,3",1, kFloatDataProcessing3, 0x1f000000) 454/* MOP_dmadd */ 455DEFINE_MOP(MOP_dmadd, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},CANTHROW,kLtFpmac,"fmadd","0,1,2,3",1, kFloatDataProcessing3, 0x1f400000) 456 457/* MOP_smsub */ 458DEFINE_MOP(MOP_smsub, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},CANTHROW,kLtFpmac,"fmsub","0,1,2,3",1, kFloatDataProcessing3, 0x1f008000) 459/* MOP_dmsub */ 460DEFINE_MOP(MOP_dmsub, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},CANTHROW,kLtFpmac,"fmsub","0,1,2,3",1, kFloatDataProcessing3, 0x1f408000) 461 462/* MOP_snmul */ 463DEFINE_MOP(MOP_snmul, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS},CANTHROW,kLtFpmul,"fnmul","0,1,2",1, kFloatDataProcessing2, 0x1e208800) 464/* MOP_dnmul */ 465DEFINE_MOP(MOP_dnmul, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS},CANTHROW,kLtFpmul,"fnmul","0,1,2",1, kFloatDataProcessing2, 0x1e608800) 466 467/* MOP_hcselrrrc --- Floating-point Conditional Select */ 468DEFINE_MOP(MOP_hcselrrrc, {&OpndDesc::Reg16FD,&OpndDesc::Reg16FS,&OpndDesc::Reg16FS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtFpalu,"fcsel","0,1,2,3",1,kFloatCondSelect,0x1ee00c00) 469/* MOP_scselrrrc */ 470DEFINE_MOP(MOP_scselrrrc, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS,&OpndDesc::Reg32FS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtFpalu,"fcsel","0,1,2,3",1,kFloatCondSelect,0x1e200c00) 471/* MOP_dcselrrrc */ 472DEFINE_MOP(MOP_dcselrrrc, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS,&OpndDesc::Reg64FS,&OpndDesc::Cond,&OpndDesc::CCS},ISCONDDEF,kLtFpalu,"fcsel","0,1,2,3",1,kFloatCondSelect,0x1e600c00) 473 474/* MOP_wldli -- load 32-bit literal */ 475DEFINE_MOP(MOP_wldli, {&OpndDesc::Reg32ID,&OpndDesc::AddressName},ISLOAD|CANTHROW,kLtLoad1,"ldr","0,1",1,kLoadLiteralReg,0x18000000) 476/* MOP_xldli -- load 64-bit literal */ 477DEFINE_MOP(MOP_xldli, {&OpndDesc::Reg64ID,&OpndDesc::AddressName},ISLOAD|CANTHROW,kLtLoad2,"ldr","0,1",1,kLoadLiteralReg,0x58000000) 478/* MOP_sldli -- load 32-bit literal */ 479DEFINE_MOP(MOP_sldli, {&OpndDesc::Reg32FD,&OpndDesc::AddressName},ISLOAD|CANTHROW,kLtLoad1,"ldr","0,1",1,kLoadLiteralReg,0x1c000000) 480/* MOP_dldli -- load 64-bit literal */ 481DEFINE_MOP(MOP_dldli, {&OpndDesc::Reg64FD,&OpndDesc::AddressName},ISLOAD|CANTHROW,kLtLoad2,"ldr","0,1",1,kLoadLiteralReg,0x5c000000) 482 483/* AArch64 branches/calls */ 484/* MOP_xbl -- branch with link (call); this is a special definition */ 485DEFINE_MOP(MOP_xbl, {&OpndDesc::AddressName,&OpndDesc::ListSrc},ISCALL|CANTHROW,kLtBranch,"bl","0",1,kBranchImm,0x94000000) 486/* MOP_xblr -- branch with link (call) to register; this is a special definition */ 487DEFINE_MOP(MOP_xblr, {&OpndDesc::Reg64IS,&OpndDesc::ListSrc},ISCALL|CANTHROW,kLtBranch,"blr","0",1,kBranchReg,0xd63f0000) 488 489/* Tls descriptor */ 490/* 491 * add x0, #:tprel_hi12:symbol, lsl #12 492 * add x0, #:tprel_lo12_nc:symbol 493 */ 494DEFINE_MOP(MOP_tls_desc_rel, {&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::LiteralSrc},SPINTRINSIC,kLtAlu,"tlsdescrel","0,1",2) 495 496/* 497 * adrp x0, , :tlsdesc:symbol 498 * ldr x1, [x0, #tlsdesc_lo12:symbol]] 499 * add x0, #tlsdesc_lo12:symbol 500 * .tlsdesccall symbol 501 * blr x1 502 */ 503DEFINE_MOP(MOP_tls_desc_call, {&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::ListSrc},ISCALL|CANTHROW|SPINTRINSIC,kLtBranch,"tlsdesccall","0",2) 504 505/* 506 * release registers occupied by MOP_tls_desc_call 507 */ 508DEFINE_MOP(MOP_pseduo_tls_release, {&OpndDesc::Reg64IS}, 0,kLtUndef,"pseudo_tls_release","0",0) 509 510/* System register access */ 511/* MOP_mrs */ 512DEFINE_MOP(MOP_mrs, {&OpndDesc::Reg64ID,&OpndDesc::String0S},ISMOVE,kLtAlu,"mrs","0,1",1, kSystemInsn, 0xd53bd040) 513 514 515/* Inline asm */ 516/* Number of instructions generated by inline asm is arbitrary. Use a large number here. */ 517/* asm string, output list, clobber list, input list, output constraint, input constraint, out reg prefix, in reg prefix */ 518DEFINE_MOP(MOP_asm, {&OpndDesc::String0S,&OpndDesc::ListDest,&OpndDesc::ListDest,&OpndDesc::ListSrc,&OpndDesc::ListSrc,&OpndDesc::ListSrc,&OpndDesc::ListSrc,&OpndDesc::ListSrc},INLINEASM|CANTHROW|HASACQUIRE|HASRELEASE,kLtUndef,"asm","0,1,2,3",100) 519 520/* c sync builtins */ 521/* 522 * intrinsic_sync_lock_test_setI w0, w1, x2, w3, lable1 523 * label1: 524 * ldxr w0, [x2] 525 * stxr w1, w3, [x2] 526 * cbnz w1, label1 527 * dmb ish 528 */ 529DEFINE_MOP(MOP_sync_lock_test_setI, {&OpndDesc::Reg32ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_sync_lock_test_setI","0,1,2,3,4",5) 530 531/* 532 * intrinsic_sync_lock_test_setL x0, w1, x2, x3, lable1 533 * label1: 534 * ldxr x0, [x2] 535 * stxr w1, x3, [x2] 536 * cbnz w1, label1 537 * dmb ish 538 */ 539DEFINE_MOP(MOP_sync_lock_test_setL, {&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_sync_lock_test_setL","0,1,2,3,4",5) 540 541/* AARCH64 LOADS */ 542/* MOP_wldrsb --- Load Register Signed Byte */ 543DEFINE_MOP(MOP_wldrsb, {&OpndDesc::Reg32ID,&OpndDesc::Mem8S},ISLOAD|CANTHROW,kLtLoad1,"ldrsb","0,1",1,MOP_wldrsbValid,MOP_wldrsbSplit,kLoadStoreReg,0x38c00000) 544/* MOP_xldrsb --- Load Register Signed Byte */ 545DEFINE_MOP(MOP_xldrsb, {&OpndDesc::Reg64ID,&OpndDesc::Mem8S},ISLOAD|CANTHROW,kLtLoad1,"ldrsb","0,1",1,MOP_xldrsbValid,MOP_xldrsbSplit,kLoadStoreReg,0x38800000) 546/* MOP_wldrb */ 547DEFINE_MOP(MOP_wldrb, {&OpndDesc::Reg32ID,&OpndDesc::Mem8S},ISLOAD|CANTHROW,kLtLoad1,"ldrb","0,1",1,MOP_wldrbValid,MOP_wldrbSplit,kLoadStoreReg,0x38400000) 548/* MOP_wldrsh --- Load Register Signed Halfword */ 549DEFINE_MOP(MOP_wldrsh, {&OpndDesc::Reg32ID,&OpndDesc::Mem16S},ISLOAD|CANTHROW,kLtLoad1,"ldrsh","0,1",1,MOP_wldrshValid,MOP_wldrshSplit,kLoadStoreReg,0x78c00000) 550/* MOP_xldrsh --- Load Register Signed Halfword */ 551DEFINE_MOP(MOP_xldrsh, {&OpndDesc::Reg64ID,&OpndDesc::Mem16S},ISLOAD|CANTHROW,kLtLoad1,"ldrsh","0,1",1,MOP_xldrshValid,MOP_xldrshSplit, kLoadStoreReg,0x7880000) 552/* MOP_xldrsw --- Load Register Signed Word */ 553DEFINE_MOP(MOP_xldrsw, {&OpndDesc::Reg64ID,&OpndDesc::Mem32S},ISLOAD|CANTHROW,kLtLoad1,"ldrsw","0,1",1,MOP_xldrswValid,MOP_xldrswSplit) 554/* MOP_wldrh */ 555DEFINE_MOP(MOP_wldrh, {&OpndDesc::Reg32ID, &OpndDesc::Mem16S},ISLOAD|CANTHROW,kLtLoad1,"ldrh","0,1",1,MOP_wldrhValid,MOP_wldrhSplit,kLoadStoreReg,0x78400000) 556/* MOP_wldr */ 557DEFINE_MOP(MOP_wldr, {&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|CANTHROW,kLtLoad1,"ldr","0,1",1,MOP_wldrValid,MOP_wldrSplit,kLoadStoreReg,0xb8400000) 558/* MOP_xldr */ 559DEFINE_MOP(MOP_xldr, {&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|CANTHROW,kLtLoad2,"ldr","0,1",1,MOP_xldrValid,MOP_xldrSplit,kLoadStoreReg,0xf8400000) 560/* MOP_bldr */ 561DEFINE_MOP(MOP_bldr, {&OpndDesc::Reg8FD,&OpndDesc::Mem8S},ISLOAD|CANTHROW,kLtFLoad64,"ldr","0,1",1,MOP_bldrValid,MOP_bldrSplit,kLoadStoreFloat,0x3c400000) 562/* MOP_hldr */ 563DEFINE_MOP(MOP_hldr, {&OpndDesc::Reg16FD,&OpndDesc::Mem16S},ISLOAD|CANTHROW,kLtFLoad64,"ldr","0,1",1,MOP_hldrValid,MOP_hldrSplit,kLoadStoreFloat,0x7c400000) 564/* MOP_sldr */ 565DEFINE_MOP(MOP_sldr, {&OpndDesc::Reg32FD,&OpndDesc::Mem32S},ISLOAD|CANTHROW,kLtFLoadMany,"ldr","0,1",1,MOP_sldrValid,MOP_sldrSplit,kLoadStoreFloat,0xbc400000) 566/* MOP_dldr */ 567DEFINE_MOP(MOP_dldr, {&OpndDesc::Reg64FD,&OpndDesc::Mem64S},ISLOAD|CANTHROW,kLtFLoadMany,"ldr","0,1",1,MOP_dldrValid,MOP_dldrSplit,kLoadStoreFloat,0xfc400000) 568/* MOP_qldr */ 569DEFINE_MOP(MOP_qldr, {&OpndDesc::Reg128VD,&OpndDesc::Mem128S},ISLOAD|CANTHROW,kLtFLoadMany,"ldr","0,1",1,MOP_qldrValid,MOP_qldrSplit, kLoadStoreFloat, 0x3cc00000) 570 571/* AArch64 LDP/LDPSW */ 572/* MOP_wldp */ 573DEFINE_MOP(MOP_wldp, {&OpndDesc::Reg32ID,&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|ISLOADPAIR|CANTHROW,kLtLoad2,"ldp","0,1,2",1,MOP_wldpValid,MOP_wldpSplit,kLoadPair,0x28000000) 574/* MOP_xldp */ 575DEFINE_MOP(MOP_xldp, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|ISLOADPAIR|CANTHROW,kLtLoad3plus,"ldp","0,1,2",1,MOP_xldpValid,MOP_xldpSplit,kLoadPair,0xa8000000) 576/* MOP_xldpsw */ 577DEFINE_MOP(MOP_xldpsw, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Mem32S},ISLOAD|ISLOADPAIR|CANTHROW,kLtLoad2,"ldpsw","0,1,2",1,MOP_xldpswValid,MOP_xldpswSplit,kLoadPair,0x68400000) 578/* MOP_sldp */ 579DEFINE_MOP(MOP_sldp, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FD,&OpndDesc::Mem32S},ISLOAD|ISLOADPAIR|CANTHROW,kLtFLoad64,"ldp","0,1,2",1,MOP_sldpValid,MOP_sldpSplit,kLoadPairFloat,0x2c000000) 580/* MOP_dldp */ 581DEFINE_MOP(MOP_dldp, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FD,&OpndDesc::Mem64S},ISLOAD|ISLOADPAIR|CANTHROW,kLtFLoadMany,"ldp","0,1,2",1,MOP_dldpValid,MOP_dldpSplit,kLoadPairFloat,0x6c000000) 582/* MOP_qldp */ 583DEFINE_MOP(MOP_qldp, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VD,&OpndDesc::Mem128S},ISLOAD|ISLOADPAIR|CANTHROW,kLtFLoadMany,"ldp","0,1,2",1,MOP_qldpValid,MOP_qldpSplit, kLoadPairFloat, 0xac000000) 584 585/* AARCH64 Load with Acquire semantics */ 586/* MOP_wldarb */ 587DEFINE_MOP(MOP_wldarb, {&OpndDesc::Reg32ID,&OpndDesc::Mem8S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldarb","0,1",1,MOP_wldarbValid,kLoadStoreAR,0x8dffc00) 588/* MOP_wldarh */ 589DEFINE_MOP(MOP_wldarh, {&OpndDesc::Reg32ID, &OpndDesc::Mem16S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldarh","0,1",1,MOP_wldarhValid,kLoadStoreAR,0x48dffc00) 590/* MOP_wldar */ 591DEFINE_MOP(MOP_wldar, {&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldar","0,1",1,MOP_wldarValid,kLoadStoreAR,0x88dffc00) 592/* MOP_xldar */ 593DEFINE_MOP(MOP_xldar, {&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldar","0,1",1,MOP_xldarValid,kLoadStoreAR,0xc8dffc00) 594 595/* MOP_wmovkri16 */ 596DEFINE_MOP(MOP_wmovkri16, {&OpndDesc::Reg32IDS,&OpndDesc::Imm16,&OpndDesc::Lsl4},ISMOVE,kLtShift,"movk","0,1,2",1,MOP_wmovkri16Valid,kMoveWide,0x72800000) 597/* MOP_xmovkri16 */ 598DEFINE_MOP(MOP_xmovkri16, {&OpndDesc::Reg64IDS,&OpndDesc::Imm16,&OpndDesc::Lsl6},ISMOVE,kLtShift,"movk","0,1,2",1,MOP_xmovkri16Valid,kMoveWide,0xf2800000) 599 600/* MOP_wmovzri16 */ 601DEFINE_MOP(MOP_wmovzri16, {&OpndDesc::Reg32ID,&OpndDesc::Imm16,&OpndDesc::Lsl4},ISMOVE,kLtShift,"movz","0,1,2",1,MOP_wmovzri16Valid,kMoveWide,0x52800000) 602/* MOP_xmovzri16 */ 603DEFINE_MOP(MOP_xmovzri16, {&OpndDesc::Reg64ID,&OpndDesc::Imm16,&OpndDesc::Lsl6},ISMOVE,kLtShift,"movz","0,1,2",1,MOP_xmovzri16Valid,kMoveWide,0xd2800000) 604 605/* MOP_wmovnri16 */ 606DEFINE_MOP(MOP_wmovnri16, {&OpndDesc::Reg32ID,&OpndDesc::Imm16,&OpndDesc::Lsl4},ISMOVE,kLtShift,"movn","0,1,2",1,MOP_wmovnri16Valid,kMoveWide,0x12800000) 607/* MOP_xmovnri16 */ 608DEFINE_MOP(MOP_xmovnri16, {&OpndDesc::Reg64ID,&OpndDesc::Imm16,&OpndDesc::Lsl6},ISMOVE,kLtShift,"movn","0,1,2",1,MOP_xmovnri16Valid,kMoveWide,0x92800000) 609 610/* AARCH64 Load exclusive with/without acquire semantics */ 611DEFINE_MOP(MOP_wldxrb, {&OpndDesc::Reg32ID,&OpndDesc::Mem8S},ISLOAD|ISATOMIC|CANTHROW,kLtLoad1,"ldxrb","0,1",1,MOP_wldxrbValid,kLoadExclusive,0x85f7c00) 612DEFINE_MOP(MOP_wldxrh, {&OpndDesc::Reg32ID,&OpndDesc::Mem16S},ISLOAD|ISATOMIC|CANTHROW,kLtLoad1,"ldxrh","0,1",1,MOP_wldxrhValid,kLoadExclusive,0x485f7c00) 613DEFINE_MOP(MOP_wldxr, {&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|ISATOMIC|CANTHROW,kLtLoad1,"ldxr","0,1",1,MOP_wldxrValid,kLoadExclusive,0x885f7c00) 614DEFINE_MOP(MOP_xldxr, {&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|ISATOMIC|CANTHROW,kLtLoad1,"ldxr","0,1",1,MOP_xldxrValid,kLoadExclusive,0xc85f7c00) 615 616DEFINE_MOP(MOP_wldaxrb,{&OpndDesc::Reg32ID,&OpndDesc::Mem8S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxrb","0,1",1,MOP_wldaxrbValid,kLoadExclusive,0x85ffc00) 617DEFINE_MOP(MOP_wldaxrh,{&OpndDesc::Reg32ID,&OpndDesc::Mem16S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxrh","0,1",1,MOP_wldaxrhValid,kLoadExclusive,0x485ffc00) 618DEFINE_MOP(MOP_wldaxr, {&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxr","0,1",1,MOP_wldaxrValid,kLoadExclusive,0x885ffc00) 619DEFINE_MOP(MOP_xldaxr, {&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxr","0,1",1,MOP_xldaxrValid,kLoadExclusive,0xc85ffc00) 620 621DEFINE_MOP(MOP_wldaxp, {&OpndDesc::Reg32ID,&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|ISLOADPAIR|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxp","0,1,2",1,MOP_wldaxpValid,kLoadExclusivePair,0x887f8000) 622DEFINE_MOP(MOP_xldaxp, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Mem64S},ISLOAD|ISLOADPAIR|ISATOMIC|HASACQUIRE|CANTHROW,kLtLoad1,"ldaxp","0,1,2",1,MOP_xldaxpValid,kLoadExclusivePair,0xc87f8000) 623 624/* MOP_vsqrts */ 625DEFINE_MOP(MOP_vsqrts, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"fsqrt","0,1",1,kFloatDataProcessing1,0x1e21c000) 626/* MOP_vsqrtd */ 627DEFINE_MOP(MOP_vsqrtd, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivD,"fsqrt","0,1",1,kFloatDataProcessing1,0x1e61c000) 628 629/* MOP_sfrintzrr */ 630DEFINE_MOP(MOP_sfrintzrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"frintz","0,1",1,kFloatDataProcessing1,0x1e25c000) 631/* MOP_dfrintzrr */ 632DEFINE_MOP(MOP_dfrintzrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivS,"frintz","0,1",1,kFloatDataProcessing1,0x1e65c000) 633 634/* MOP_sfrintmrr */ 635DEFINE_MOP(MOP_sfrintmrr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"frintm","0,1",1,kFloatDataProcessing1,0x1e254000) 636/* MOP_dfrintmrr */ 637DEFINE_MOP(MOP_dfrintmrr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivS,"frintm","0,1",1,kFloatDataProcessing1,0x1e654000) 638 639/* MOP_sfrintprr */ 640DEFINE_MOP(MOP_sfrintprr, {&OpndDesc::Reg32FD,&OpndDesc::Reg32FS},CANTHROW,kLtAdvsimdDivS,"frintp","0,1",1,kFloatDataProcessing1,0x1e24c000) 641/* MOP_dfrintprr */ 642DEFINE_MOP(MOP_dfrintprr, {&OpndDesc::Reg64FD,&OpndDesc::Reg64FS},CANTHROW,kLtAdvsimdDivS,"frintp","0,1",1,kFloatDataProcessing1,0x1e64c000) 643 644/* # Non Definitions */ 645/* # As far as register allocation is concerned, the instructions below are non-definitions. */ 646 647/* MOP_bcs */ 648DEFINE_MOP(MOP_bcs, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bcs","1",1, kCondBranch, 0x5400000e) 649/* MOP_bcc */ 650DEFINE_MOP(MOP_bcc, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bcc","1",1, kCondBranch, 0x5400000f) 651/* MOP_beq */ 652DEFINE_MOP(MOP_beq, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"beq","1",1,kCondBranch,0x54000000) 653/* MOP_bne */ 654DEFINE_MOP(MOP_bne, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bne","1",1,kCondBranch,0x54000001) 655/* MOP_blt */ 656DEFINE_MOP(MOP_blt, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"blt","1",1,kCondBranch,0x5400000b) 657/* MOP_ble */ 658DEFINE_MOP(MOP_ble, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"ble","1",1,kCondBranch,0x5400000d) 659/* MOP_bgt */ 660DEFINE_MOP(MOP_bgt, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bgt","1",1,kCondBranch,0x5400000c) 661/* MOP_bge */ 662DEFINE_MOP(MOP_bge, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bge","1",1,kCondBranch,0x5400000a) 663/* MOP_blo equal to MOP_blt for unsigned comparison */ 664DEFINE_MOP(MOP_blo, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"blo","1",1,kCondBranch,0x54000003) 665/* MOP_bls equal to MOP_bls for unsigned comparison */ 666DEFINE_MOP(MOP_bls, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bls","1",1,kCondBranch,0x54000009) 667/* MOP_bhs equal to MOP_bge for unsigned comparison */ 668DEFINE_MOP(MOP_bhs, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bhs","1",1,kCondBranch,0x54000002) 669/* MOP_bhi equal to MOP_bgt for float comparison */ 670DEFINE_MOP(MOP_bhi, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bhi","1",1,kCondBranch,0x54000008) 671/* MOP_bpl equal to MOP_bge for float comparison */ 672DEFINE_MOP(MOP_bpl, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bpl","1",1,kCondBranch,0x54000005) 673DEFINE_MOP(MOP_bmi, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bmi","1",1,kCondBranch,0x54000004) 674DEFINE_MOP(MOP_bvc, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bvc","1",1,kCondBranch,0x54000007) 675DEFINE_MOP(MOP_bvs, {&OpndDesc::CCS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"bvs","1",1,kCondBranch,0x54000006) 676 677/* MOP_xret AARCH64 Specific */ 678DEFINE_MOP(MOP_xret, {},CANTHROW,kLtBranch,"ret","",1,kBranchReg,0xd65f03c0) 679/* MOP_clrex AARCH64 Specific */ 680DEFINE_MOP(MOP_clrex, {},CANTHROW,kLtBranch,"clrex","",1, kBranchReg, 0xd503303f) 681 682/* AARCH64 Floating-Point COMPARES signaling versions */ 683/* MOP_hcmperi -- AArch64 cmp has no dest operand */ 684DEFINE_MOP(MOP_hcmperi, {&OpndDesc::CCD, &OpndDesc::Reg16FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1ee02018) 685/* MOP_hcmperr -- register, shifted register, AArch64 cmp has no dest operand */ 686DEFINE_MOP(MOP_hcmperr, {&OpndDesc::CCD, &OpndDesc::Reg16FS,&OpndDesc::Reg16FS},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1ee02010) 687 688/* MOP_scmperi -- AArch64 cmp has no dest operand */ 689DEFINE_MOP(MOP_scmperi, {&OpndDesc::CCD, &OpndDesc::Reg32FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1e202018) 690/* MOP_scmperr */ 691DEFINE_MOP(MOP_scmperr, {&OpndDesc::CCD, &OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1e202010) 692 693/* MOP_dcmperi -- AArch64 cmp has no dest operand */ 694DEFINE_MOP(MOP_dcmperi, {&OpndDesc::CCD, &OpndDesc::Reg64FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1e602018) 695/* MOP_dcmperr */ 696DEFINE_MOP(MOP_dcmperr, {&OpndDesc::CCD, &OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fcmpe","1,2",1,kFloatCompare,0x1e602010) 697 698/* AARCH64 Floating-Point COMPARES non-signaling (quiet) versions */ 699/* MOP_hcmpqri -- AArch64 cmp has no dest operand */ 700DEFINE_MOP(MOP_hcmpqri, {&OpndDesc::CCD, &OpndDesc::Reg16FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1ee02008) 701/* MOP_hcmpqrr -- register, shifted register, AArch64 cmp has no dest operand */ 702DEFINE_MOP(MOP_hcmpqrr, {&OpndDesc::CCD, &OpndDesc::Reg16FS,&OpndDesc::Reg16FS},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1ee02000) 703 704/* MOP_scmpqri -- AArch64 cmp has no dest operand */ 705DEFINE_MOP(MOP_scmpqri, {&OpndDesc::CCD, &OpndDesc::Reg32FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1e202008) 706/* MOP_scmpqrr */ 707DEFINE_MOP(MOP_scmpqrr, {&OpndDesc::CCD, &OpndDesc::Reg32FS,&OpndDesc::Reg32FS},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1e202000) 708 709/* MOP_dcmpqri -- AArch64 cmp has no dest operand */ 710DEFINE_MOP(MOP_dcmpqri, {&OpndDesc::CCD, &OpndDesc::Reg64FS,&OpndDesc::FpImm8},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1e602008) 711/* MOP_dcmpqrr */ 712DEFINE_MOP(MOP_dcmpqrr, {&OpndDesc::CCD, &OpndDesc::Reg64FS,&OpndDesc::Reg64FS},0,kLtFpalu,"fcmp","1,2",1,kFloatCompare,0x1e602000) 713 714/* AARCH64 Integer COMPARES */ 715/* MOP_wcmpri -- AArch64 cmp has no dest operand */ 716DEFINE_MOP(MOP_wcmpri, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"cmp","1,2",1,MOP_wcmpriValid,kAddSubImm,0x7100001f) 717/* MOP_wcmprr -- register, shifted register, AArch64 cmp has no dest operand */ 718DEFINE_MOP(MOP_wcmprr, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"cmp","1,2",1,kAddSubReg,0x6b00001f) 719/* MOP_wcmprrs -- register, shifted register, AArch64 cmp has no dest operand */ 720DEFINE_MOP(MOP_wcmprrs, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAlu,"cmp","1,2,3",1,MOP_wcmprrsValid,kAddSubShiftReg, 0x6b00001f) 721/* MOP_wwcmprre -- register, shifted register, AArch64 cmp has no dest operand */ 722DEFINE_MOP(MOP_wwcmprre, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAlu,"cmp","1,2,3",1,MOP_wwcmprreValid,kAddSubExtendReg, 0x6b20001f) 723/* MOP_xcmpri -- AArch64 cmp has no dest operand */ 724DEFINE_MOP(MOP_xcmpri, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Imm16},0,kLtAlu,"cmp","1,2",1,MOP_xcmpriValid,kAddSubImm,0xf100001f) 725/* MOP_xcmprr -- register, shifted register, AArch64 cmp has no dest operand */ 726DEFINE_MOP(MOP_xcmprr, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"cmp","1,2",1,kAddSubReg,0xeb00001f) 727/* MOP_xcmprrs -- register, shifted register, AArch64 cmp has no dest operand */ 728DEFINE_MOP(MOP_xcmprrs, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAlu,"cmp","1,2,3",1,MOP_xcmprrsValid,kAddSubShiftReg, 0xeb00001f) 729/* MOP_xwcmprre -- register, shifted register, AArch64 cmp has no dest operand */ 730DEFINE_MOP(MOP_xwcmprre, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAlu,"cmp","1,2,3",1,MOP_xwcmprreValid,kAddSubExtendReg, 0xeb20001f) 731 732/* MOP_wccmpriic -- AArch64 cmp has no dest operand */ 733DEFINE_MOP(MOP_wccmpriic, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Imm5,&OpndDesc::Imm4,&OpndDesc::Cond,&OpndDesc::CCS},0,kLtAlu,"ccmp","1,2,3,4",1,MOP_wccmpriicValid,MOP_wccmpriicSplit,kCondCompareImm,0x7a400800) 734/* MOP_wccmprric -- register, shifted register, AArch64 cmp has no dest operand */ 735DEFINE_MOP(MOP_wccmprric, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Imm4,&OpndDesc::Cond,&OpndDesc::CCS},0,kLtAlu,"ccmp","1,2,3,4",1,MOP_wccmprricValid,kCondCompareReg,0x7a400000) 736/* MOP_xccmpriic -- AArch64 cmp has no dest operand */ 737DEFINE_MOP(MOP_xccmpriic, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Imm5,&OpndDesc::Imm4,&OpndDesc::Cond,&OpndDesc::CCS},0,kLtAlu,"ccmp","1,2,3,4",1,MOP_xccmpriicValid,MOP_xccmpriicSplit,kCondCompareImm,0xfa400800) 738/* MOP_xccmprric -- register, shifted register, AArch64 cmp has no dest operand */ 739DEFINE_MOP(MOP_xccmprric, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Imm4,&OpndDesc::Cond,&OpndDesc::CCS},0,kLtAlu,"ccmp","1,2,3,4",1,MOP_xccmprricValid,kCondCompareReg,0xfa400000) 740 741/* MOP_wcmnri -- AArch64 cmp has no dest operand */ 742DEFINE_MOP(MOP_wcmnri, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Imm12},0,kLtAlu,"cmn","1,2",1,MOP_wcmnriValid,kAddSubImm,0x3100001f) 743/* MOP_wcmnrr -- register, shifted register, AArch64 cmp has no dest operand */ 744DEFINE_MOP(MOP_wcmnrr, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS},0,kLtAlu,"cmn","1,2",1,kAddSubReg,0x2b00001f) 745/* MOP_wcmnrrs -- register, shifted register, AArch64 cmp has no dest operand */ 746DEFINE_MOP(MOP_wcmnrrs, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Bitshift32},0,kLtAlu,"cmn","1,2,3",1,MOP_wcmnrrsValid,kAddSubShiftReg, 0x2b00001f) 747/* MOP_wwcmnrre -- register, shifted register, AArch64 cmp has no dest operand */ 748DEFINE_MOP(MOP_wwcmnrre, {&OpndDesc::CCD, &OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAlu,"cmn","1,2,3",1,MOP_wwcmnrreValid,kAddSubExtendReg, 0x2b20001f) 749/* MOP_xcmnri -- AArch64 cmp has no dest operand */ 750DEFINE_MOP(MOP_xcmnri, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Imm16},0,kLtAlu,"cmn","1,2",1,MOP_xcmnriValid,kAddSubImm,0xb100001f) 751/* MOP_xcmnrr -- register, shifted register, AArch64 cmp has no dest operand */ 752DEFINE_MOP(MOP_xcmnrr, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg64IS},0,kLtAlu,"cmn","1,2",1,kAddSubReg,0xab00001f) 753/* MOP_xcmnrrs -- register, shifted register, AArch64 cmp has no dest operand */ 754DEFINE_MOP(MOP_xcmnrrs, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Bitshift64},0,kLtAlu,"cmn","1,2,3",1,MOP_xcmnrrsValid,kAddSubShiftReg, 0xab00001f) 755/* MOP_xwcmnrre -- register, shifted register, AArch64 cmp has no dest operand */ 756DEFINE_MOP(MOP_xwcmnrre, {&OpndDesc::CCD, &OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::Extendshift64},0,kLtAlu,"cmn","1,2,3",1,MOP_xwcmnrreValid,kAddSubExtendReg, 0xab20001f) 757 758/* AArch64 branches */ 759/* MOP_xbr -- branch to register */ 760DEFINE_MOP(MOP_xbr, {&OpndDesc::Reg64IS,&OpndDesc::LiteralSrc},ISUNCONDBRANCH,kLtBranch,"br","0",1,kBranchReg,0xd61f0000) 761/* MOP_Tbbuncond */ 762DEFINE_MOP(MOP_xuncond, {&OpndDesc::AddressName},ISUNCONDBRANCH,kLtBranch,"b","0",1,kBranchImm,0x14000000) 763 764/* MOP_wcbnz --- Compare and Branch on Nonzero */ 765DEFINE_MOP(MOP_wcbnz, {&OpndDesc::Reg32IS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"cbnz","0,1",1,kCompareBranch,0x35000000) 766/* MOP_xcbnz */ 767DEFINE_MOP(MOP_xcbnz, {&OpndDesc::Reg64IS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"cbnz","0,1",1,kCompareBranch,0xb5000000) 768/* MOP_wcbz --- Compare and Branch on zero */ 769DEFINE_MOP(MOP_wcbz, {&OpndDesc::Reg32IS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"cbz","0,1",1,kCompareBranch,0x34000000) 770/* MOP_xcbz */ 771DEFINE_MOP(MOP_xcbz, {&OpndDesc::Reg64IS,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"cbz","0,1",1,kCompareBranch,0xb4000000) 772 773/* MOP_wtbnz --- Test bit and Branch if Nonzero */ 774DEFINE_MOP(MOP_wtbnz, {&OpndDesc::Reg32IS,&OpndDesc::Imm8,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"tbnz","0,1,2",1,MOP_wtbnzValid,kTestBranch,0x37000000) 775/* MOP_xtbnz */ 776DEFINE_MOP(MOP_xtbnz, {&OpndDesc::Reg64IS,&OpndDesc::Imm8,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"tbnz","0,1,2",1,MOP_xtbnzValid,kTestBranch,0xb7000000) 777/* MOP_wtbz --- Test bit and Branch if Zero */ 778DEFINE_MOP(MOP_wtbz, {&OpndDesc::Reg32IS,&OpndDesc::Imm8,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"tbz","0,1,2",1,MOP_wtbzValid,kTestBranch,0x36000000) 779/* MOP_xtbz */ 780DEFINE_MOP(MOP_xtbz, {&OpndDesc::Reg64IS,&OpndDesc::Imm8,&OpndDesc::AddressName},ISCONDBRANCH,kLtBranch,"tbz","0,1,2",1,MOP_xtbzValid,kTestBranch,0xb6000000) 781 782/* AARCH64 STORES */ 783/* MOP_wstrb -- Store Register Byte */ 784DEFINE_MOP(MOP_wstrb, {&OpndDesc::Reg32IS,&OpndDesc::Mem8D},ISSTORE|CANTHROW,kLtStore1,"strb","0,1",1,MOP_wstrbValid,MOP_wstrbSplit,kLoadStoreReg,0x38000000) 785/* MOP_wstrh -- Store Register Halfword */ 786DEFINE_MOP(MOP_wstrh, {&OpndDesc::Reg32IS,&OpndDesc::Mem16D},ISSTORE|CANTHROW,kLtStore1,"strh","0,1",1,MOP_wstrhValid,MOP_wstrhSplit,kLoadStoreReg,0x78000000) 787/* MOP_wstr -- Store Register Word */ 788DEFINE_MOP(MOP_wstr, {&OpndDesc::Reg32IS,&OpndDesc::Mem32D},ISSTORE|CANTHROW,kLtStore1,"str","0,1",1,MOP_wstrValid,MOP_wstrSplit,kLoadStoreReg,0xb8000000) 789/* MOP_xstr -- Store Register Double word */ 790DEFINE_MOP(MOP_xstr, {&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|CANTHROW,kLtStore2,"str","0,1",1,MOP_xstrValid,MOP_xstrSplit,kLoadStoreReg,0xf8000000) 791 792/* MOP_sstr -- Store Register SIMD/FP Float */ 793DEFINE_MOP(MOP_sstr, {&OpndDesc::Reg32FS,&OpndDesc::Mem32D},ISSTORE|CANTHROW,kLtStore2,"str","0,1",1,MOP_sstrValid,MOP_sstrSplit,kLoadStoreFloat,0xbc000000) 794/* MOP_dstr -- Store Register SIMD/FP Double */ 795DEFINE_MOP(MOP_dstr, {&OpndDesc::Reg64FS,&OpndDesc::Mem64D},ISSTORE|CANTHROW,kLtStore3plus,"str","0,1",1,MOP_dstrValid,MOP_dstrSplit,kLoadStoreFloat,0xfc000000) 796/* MOP_qstr -- Store Register SIMD/FP Double */ 797DEFINE_MOP(MOP_qstr, {&OpndDesc::Reg128VS,&OpndDesc::Mem128D},ISSTORE|CANTHROW,kLtStore3plus,"str","0,1",1,MOP_qstrValid,MOP_qstrSplit, kLoadStoreFloat, 0x3c800000) 798 799/* AArch64 STP. */ 800/* MOP_wstp */ 801DEFINE_MOP(MOP_wstp, {&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Mem32D},ISSTORE|ISSTOREPAIR|CANTHROW,kLtStore2,"stp","0,1,2",1,MOP_wstpValid,MOP_wstpSplit,kStorePair,0x28000000) 802/* MOP_xstp */ 803DEFINE_MOP(MOP_xstp, {&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|ISSTOREPAIR|CANTHROW,kLtStore3plus,"stp","0,1,2",1,MOP_xstpValid,MOP_xstpSplit,kStorePair,0xa8000000) 804/* AArch64 does not define STPSW. It has no practical value. */ 805/* MOP_sstp */ 806DEFINE_MOP(MOP_sstp, {&OpndDesc::Reg32FS,&OpndDesc::Reg32FS,&OpndDesc::Mem32D},ISSTORE|ISSTOREPAIR|CANTHROW,kLtAdvsimdMulQ,"stp","0,1,2",1,MOP_sstpValid,MOP_sstpSplit,kStorePairFloat,0x2c000000) 807/* MOP_dstp */ 808DEFINE_MOP(MOP_dstp, {&OpndDesc::Reg64FS,&OpndDesc::Reg64FS,&OpndDesc::Mem64D},ISSTORE|ISSTOREPAIR|CANTHROW,kLtAdvsimdMulQ,"stp","0,1,2",1,MOP_dstpValid,MOP_dstpSplit,kStorePairFloat,0x6c000000) 809/* MOP_qstp */ 810DEFINE_MOP(MOP_qstp, {&OpndDesc::Reg128VS,&OpndDesc::Reg128VS,&OpndDesc::Mem128D},ISSTORE|ISSTOREPAIR|CANTHROW,kLtAdvsimdMulQ,"stp","0,1,2",1,MOP_qstpValid,MOP_qstpSplit, kStorePairFloat, 0xac000000) 811 812/* AARCH64 Store with Release semantics */ 813/* MOP_wstlrb -- Store-Release Register Byte */ 814DEFINE_MOP(MOP_wstlrb, {&OpndDesc::Reg32IS,&OpndDesc::Mem8D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlrb","0,1",1,MOP_wstlrbValid,kLoadStoreAR,0x89ffc00) 815/* MOP_wstlrh -- Store-Release Register Halfword */ 816DEFINE_MOP(MOP_wstlrh, {&OpndDesc::Reg32IS,&OpndDesc::Mem16D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlrh","0,1",1,MOP_wstlrhValid,kLoadStoreAR,0x489ffc00) 817/* MOP_wstlr -- Store-Release Register Word */ 818DEFINE_MOP(MOP_wstlr, {&OpndDesc::Reg32IS,&OpndDesc::Mem32D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlr","0,1",1,MOP_wstlrValid,kLoadStoreAR,0x889ffc00) 819/* MOP_xstlr -- Store-Release Register Double word */ 820DEFINE_MOP(MOP_xstlr, {&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlr","0,1",1,MOP_xstlrValid,kLoadStoreAR,0xc89ffc00) 821 822/* AARCH64 Store exclusive with/without release semantics */ 823DEFINE_MOP(MOP_wstxrb, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem8D},ISSTORE|ISATOMIC|CANTHROW,kLtStore1,"stxrb","0,1,2",1,MOP_wstxrbValid,kStoreExclusive,0x8007c00) 824DEFINE_MOP(MOP_wstxrh, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem16D},ISSTORE|ISATOMIC|CANTHROW,kLtStore1,"stxrh","0,1,2",1,MOP_wstxrhValid,kStoreExclusive,0x48007c00) 825DEFINE_MOP(MOP_wstxr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem32D},ISSTORE|ISATOMIC|CANTHROW,kLtStore1,"stxr","0,1,2",1,MOP_wstxrValid,kStoreExclusive,0x88007c00) 826DEFINE_MOP(MOP_xstxr, {&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|ISATOMIC|CANTHROW,kLtStore1,"stxr","0,1,2",1,MOP_xstxrValid,kStoreExclusive,0xc8007c00) 827 828DEFINE_MOP(MOP_wstlxrb,{&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem8D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxrb","0,1,2",1,MOP_wstlxrbValid,kStoreExclusive,0x800fc00) 829DEFINE_MOP(MOP_wstlxrh,{&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem16D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxrh","0,1,2",1,MOP_wstlxrhValid,kStoreExclusive,0x4800fc00) 830DEFINE_MOP(MOP_wstlxr, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Mem32D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxr","0,1,2",1,MOP_wstlxrValid,kStoreExclusive,0x8800fc00) 831DEFINE_MOP(MOP_xstlxr, {&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxr","0,1,2",1,MOP_xstlxrValid,kStoreExclusive,0xc800fc00) 832 833DEFINE_MOP(MOP_wstlxp, {&OpndDesc::Reg32ID,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::Mem64D},ISSTORE|ISSTOREPAIR|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxp","0,1,2,3",1,MOP_wstlxpValid,kStoreExclusivePair,0x88208000) 834DEFINE_MOP(MOP_xstlxp, {&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Mem64D},ISSTORE|ISSTOREPAIR|ISATOMIC|HASRELEASE|CANTHROW,kLtStore1,"stlxp","0,1,2,3",1,MOP_xstlxpValid,kStoreExclusivePair,0xc8208000) 835 836/* Generate a breakpoint instruction exception */ 837DEFINE_MOP(MOP_brk, {&OpndDesc::Imm16},0, kLtAlu,"brk","0",1,MOP_brkValid,kBrkInsn,0xd4200000) 838 839/* Memory barriers */ 840/* MOP_dmb_ishld */ 841DEFINE_MOP(MOP_dmb_ishld, {}, HASACQUIRE|ISDMB,kLtBranch, "dmb\tishld", "",1,kSystemInsn,0xd50339bf) 842/* MOP_dmb_ishst */ 843DEFINE_MOP(MOP_dmb_ishst, {}, HASRELEASE|ISDMB,kLtBranch, "dmb\tishst", "",1,kSystemInsn,0xd5033abf) 844/* MOP_dmb_ish */ 845DEFINE_MOP(MOP_dmb_ish, {}, HASACQUIRE|HASRELEASE|ISDMB,kLtBranch, "dmb\tish", "",1,kSystemInsn,0xd5033bbf) 846 847/* Neon simd, r:nonvector reg, u:64b vector reg, v:128b vector reg */ 848/* Following ISMOVE vector instructions must be in a group, starting with vmovui and end with vmovvv */ 849DEFINE_MOP(MOP_vmovui, {&OpndDesc::Reg64VD,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"movi","0,1",1) 850DEFINE_MOP(MOP_vmovvi, {&OpndDesc::Reg128VD,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"movi","0,1",1) 851DEFINE_MOP(MOP_vmovuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISMOVE|ISVECTOR,kLtFpalu,"mov","0,1",1) 852DEFINE_MOP(MOP_vmovvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISMOVE|ISVECTOR,kLtFpalu,"mov","0,1",1) 853DEFINE_MOP(MOP_vwmovru, {&OpndDesc::Reg32ID,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"umov","0,1",1) 854DEFINE_MOP(MOP_vwmovrv, {&OpndDesc::Reg32ID,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"umov","0,1",1) 855DEFINE_MOP(MOP_vxmovrv, {&OpndDesc::Reg64ID,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"umov","0,1",1) 856DEFINE_MOP(MOP_vwdupur, {&OpndDesc::Reg64VD,&OpndDesc::Reg32IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"dup","0,1",1) 857DEFINE_MOP(MOP_vwdupvr, {&OpndDesc::Reg128VD,&OpndDesc::Reg32IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"dup","0,1",1) 858DEFINE_MOP(MOP_vxdupur, {&OpndDesc::Reg64VD,&OpndDesc::Reg64IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"dup","0,1",1) 859DEFINE_MOP(MOP_vxdupvr, {&OpndDesc::Reg128VD,&OpndDesc::Reg64IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"dup","0,1",1) 860DEFINE_MOP(MOP_vduprv, {&OpndDesc::Reg64FD,&OpndDesc::Reg128VS},ISVECTOR|SPINTRINSIC,kLtFpalu,"dup","0,1",1) 861DEFINE_MOP(MOP_vextuuui,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"ext","0,1,2,3",1) 862DEFINE_MOP(MOP_vextvvvi,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"ext","0,1,2,3",1) 863DEFINE_MOP(MOP_vsabdlvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"sabdl","0,1,2",1) 864DEFINE_MOP(MOP_vuabdlvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"uabdl","0,1,2",1) 865DEFINE_MOP(MOP_vsabdl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"sabdl2","0,1,2",1) 866DEFINE_MOP(MOP_vuabdl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"uabdl2","0,1,2",1) 867DEFINE_MOP(MOP_vspadaluu,{&OpndDesc::Reg64VDS,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"sadalp","0,1",1) 868DEFINE_MOP(MOP_vspadalvv,{&OpndDesc::Reg128VDS,&OpndDesc::Reg128VS},ISVECTOR,kLtAlu,"sadalp","0,1",1) 869DEFINE_MOP(MOP_vupadaluu,{&OpndDesc::Reg64VDS,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"uadalp","0,1",1) 870DEFINE_MOP(MOP_vupadalvv,{&OpndDesc::Reg128VDS,&OpndDesc::Reg128VS},ISVECTOR,kLtAlu,"uadalp","0,1",1) 871DEFINE_MOP(MOP_vspadduu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"saddlp","0,1",1) 872DEFINE_MOP(MOP_vspaddvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtAlu,"saddlp","0,1",1) 873DEFINE_MOP(MOP_vupadduu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtAlu,"uaddlp","0,1",1) 874DEFINE_MOP(MOP_vupaddvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtAlu,"uaddlp","0,1",1) 875DEFINE_MOP(MOP_vwinsur, {&OpndDesc::Reg64VDS,&OpndDesc::Reg32IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"ins","0,1",1) 876DEFINE_MOP(MOP_vxinsur, {&OpndDesc::Reg64VDS,&OpndDesc::Reg64IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"ins","0,1",1) 877DEFINE_MOP(MOP_vwinsvr, {&OpndDesc::Reg128VDS,&OpndDesc::Reg32IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"ins","0,1",1) 878DEFINE_MOP(MOP_vxinsvr, {&OpndDesc::Reg128VDS,&OpndDesc::Reg64IS},ISVECTOR|SPINTRINSIC,kLtFpalu,"ins","0,1",1) 879DEFINE_MOP(MOP_vrev16dd,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"rev16","0,1",1) 880DEFINE_MOP(MOP_vrev32dd,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"rev32","0,1",1) 881DEFINE_MOP(MOP_vrev64dd,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"rev64","0,1",1) 882DEFINE_MOP(MOP_vrev16qq,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"rev16","0,1",1) 883DEFINE_MOP(MOP_vrev32qq,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"rev32","0,1",1) 884DEFINE_MOP(MOP_vrev64qq,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"rev64","0,1",1) 885DEFINE_MOP(MOP_vbaddvru,{&OpndDesc::Reg8FD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 886DEFINE_MOP(MOP_vhaddvru,{&OpndDesc::Reg16FD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 887DEFINE_MOP(MOP_vsaddvru,{&OpndDesc::Reg32FD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 888DEFINE_MOP(MOP_vbaddvrv,{&OpndDesc::Reg8FD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 889DEFINE_MOP(MOP_vhaddvrv,{&OpndDesc::Reg16FD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 890DEFINE_MOP(MOP_vsaddvrv,{&OpndDesc::Reg32FD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"addv","0,1",1) 891DEFINE_MOP(MOP_vdaddvrv,{&OpndDesc::Reg64FD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"addp","0,1",1) 892 893DEFINE_MOP(MOP_vzcmequu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmeq","0,1,2",1) 894DEFINE_MOP(MOP_vzcmgtuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmgt","0,1,2",1) 895DEFINE_MOP(MOP_vzcmgeuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmge","0,1,2",1) 896DEFINE_MOP(MOP_vzcmltuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmlt","0,1,2",1) 897DEFINE_MOP(MOP_vzcmleuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmle","0,1,2",1) 898DEFINE_MOP(MOP_vzcmeqvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmeq","0,1,2",1) 899DEFINE_MOP(MOP_vzcmgtvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmgt","0,1,2",1) 900DEFINE_MOP(MOP_vzcmgevv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmge","0,1,2",1) 901DEFINE_MOP(MOP_vzcmltvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmlt","0,1,2",1) 902DEFINE_MOP(MOP_vzcmlevv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"cmle","0,1,2",1) 903DEFINE_MOP(MOP_vcmequuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"cmeq","0,1,2",1) 904DEFINE_MOP(MOP_vcmgeuuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"cmge","0,1,2",1) 905DEFINE_MOP(MOP_vcmgtuuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"cmgt","0,1,2",1) 906DEFINE_MOP(MOP_vcmhiuuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"cmhi","0,1,2",1) 907DEFINE_MOP(MOP_vcmhsuuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"cmhs","0,1,2",1) 908DEFINE_MOP(MOP_vcmeqvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"cmeq","0,1,2",1) 909DEFINE_MOP(MOP_vcmgevvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"cmge","0,1,2",1) 910DEFINE_MOP(MOP_vcmgtvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"cmgt","0,1,2",1) 911DEFINE_MOP(MOP_vcmhivvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"cmhi","0,1,2",1) 912DEFINE_MOP(MOP_vcmhsvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"cmhs","0,1,2",1) 913DEFINE_MOP(MOP_vbsluuu,{&OpndDesc::Reg64VDS,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"bsl","0,1,2",1) 914DEFINE_MOP(MOP_vbslvvv,{&OpndDesc::Reg128VDS,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"bsl","0,1,2",1) 915 916DEFINE_MOP(MOP_vshluuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"sshl","0,1,2",1) 917DEFINE_MOP(MOP_vshlvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"sshl","0,1,2",1) 918DEFINE_MOP(MOP_vushluuu,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"ushl","0,1,2",1) 919DEFINE_MOP(MOP_vushlvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"ushl","0,1,2",1) 920 921DEFINE_MOP(MOP_vushluui,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"shl","0,1,2",1) 922DEFINE_MOP(MOP_vushlvvi,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"shl","0,1,2",1) 923DEFINE_MOP(MOP_vushruui,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"ushr","0,1,2",1) 924DEFINE_MOP(MOP_vushrvvi,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"ushr","0,1,2",1) 925 926DEFINE_MOP(MOP_vshllvvi,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"shll","0,1,2",1) 927DEFINE_MOP(MOP_vushllvvi,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"ushll","0,1,2",1) 928DEFINE_MOP(MOP_vxtnuv, {&OpndDesc::Reg64VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"xtn","0,1",1) 929DEFINE_MOP(MOP_vsxtlvu, {&OpndDesc::Reg128VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"sxtl","0,1",1) 930DEFINE_MOP(MOP_vuxtlvu, {&OpndDesc::Reg128VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"uxtl","0,1",1) 931DEFINE_MOP(MOP_vxtn2uv, {&OpndDesc::Reg64VDS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"xtn2","0,1",1) 932DEFINE_MOP(MOP_vsxtl2vv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"sxtl2","0,1",1) 933DEFINE_MOP(MOP_vuxtl2vv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"uxtl2","0,1",1) 934 935DEFINE_MOP(MOP_vshruui, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"sshr","0,1,2",1) 936DEFINE_MOP(MOP_vshrvvi, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"sshr","0,1,2",1) 937DEFINE_MOP(MOP_vshrnuvi,{&OpndDesc::Reg64VD,&OpndDesc::Reg128VS,&OpndDesc::Imm8},ISVECTOR,kLtFpalu,"shrn","0,1,2",1) 938 939DEFINE_MOP(MOP_vtbl1vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"tbl","0,1,2",1) 940DEFINE_MOP(MOP_vsmaddvvv,{&OpndDesc::Reg128VDS,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"smlal","0,1,2",1) 941DEFINE_MOP(MOP_vumaddvvv,{&OpndDesc::Reg128VDS,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"umlal","0,1,2",1) 942DEFINE_MOP(MOP_vsmullvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"smull","0,1,2",1) 943DEFINE_MOP(MOP_vumullvvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"umull","0,1,2",1) 944DEFINE_MOP(MOP_vsmull2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"smull2","0,1,2",1) 945DEFINE_MOP(MOP_vumull2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"umull2","0,1,2",1) 946DEFINE_MOP(MOP_vabsuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"abs","0,1",1) 947DEFINE_MOP(MOP_vabsvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"abs","0,1",1) 948DEFINE_MOP(MOP_vadduuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"add","0,1,2",1) 949DEFINE_MOP(MOP_vsaddlvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"saddl","0,1,2",1) 950DEFINE_MOP(MOP_vuaddlvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"uaddl","0,1,2",1) 951DEFINE_MOP(MOP_vsaddl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"saddl2","0,1,2",1) 952DEFINE_MOP(MOP_vuaddl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"uaddl2","0,1,2",1) 953DEFINE_MOP(MOP_vsaddwvvu,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"saddw","0,1,2",1) 954DEFINE_MOP(MOP_vuaddwvvu,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"uaddw","0,1,2",1) 955DEFINE_MOP(MOP_vsaddw2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"saddw2","0,1,2",1) 956DEFINE_MOP(MOP_vuaddw2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"uaddw2","0,1,2",1) 957DEFINE_MOP(MOP_vaddvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"add","0,1,2",1) 958DEFINE_MOP(MOP_vmuluuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtAdvsimdMul,"mul","0,1,2",1) 959DEFINE_MOP(MOP_vmulvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtAdvsimdMulQ,"mul","0,1,2",1) 960DEFINE_MOP(MOP_vsubuuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"sub","0,1,2",1) 961DEFINE_MOP(MOP_vsubvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"sub","0,1,2",1) 962DEFINE_MOP(MOP_vanduuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"and","0,1,2",1) 963DEFINE_MOP(MOP_vandvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"and","0,1,2",1) 964DEFINE_MOP(MOP_voruuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"orr","0,1,2",1) 965DEFINE_MOP(MOP_vorvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"orr","0,1,2",1) 966DEFINE_MOP(MOP_vxoruuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"eor","0,1,2",1) 967DEFINE_MOP(MOP_vxorvvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"eor","0,1,2",1) 968DEFINE_MOP(MOP_vnotuu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"not","0,1",1) 969DEFINE_MOP(MOP_vnotvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"not","0,1",1) 970DEFINE_MOP(MOP_vneguu, {&OpndDesc::Reg64VD,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"neg","0,1",1) 971DEFINE_MOP(MOP_vnegvv, {&OpndDesc::Reg128VD,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"neg","0,1",1) 972DEFINE_MOP(MOP_vssublvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"ssubl","0,1,2",1) 973DEFINE_MOP(MOP_vusublvuu,{&OpndDesc::Reg128VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"usubl","0,1,2",1) 974DEFINE_MOP(MOP_vssubl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"ssubl2","0,1,2",1) 975DEFINE_MOP(MOP_vusubl2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"usubl2","0,1,2",1) 976DEFINE_MOP(MOP_vssubwvvu,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"ssubw","0,1,2",1) 977DEFINE_MOP(MOP_vusubwvvu,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"usubw","0,1,2",1) 978DEFINE_MOP(MOP_vssubw2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"ssubw2","0,1,2",1) 979DEFINE_MOP(MOP_vusubw2vvv,{&OpndDesc::Reg128VD,&OpndDesc::Reg128VS,&OpndDesc::Reg128VS},ISVECTOR,kLtFpalu,"usubw2","0,1,2",1) 980DEFINE_MOP(MOP_vzip1vvv,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"zip1","0,1,2",1) 981DEFINE_MOP(MOP_vzip2vvv,{&OpndDesc::Reg64VD,&OpndDesc::Reg64VS,&OpndDesc::Reg64VS},ISVECTOR,kLtFpalu,"zip2","0,1,2",1) 982 983DEFINE_MOP(MOP_clinit, {&OpndDesc::Reg64ID,&OpndDesc::LiteralSrc},ISATOMIC|CANTHROW|ISINTRINSIC,kLtClinit,"intrinsic_clinit","0,1",4) 984 985/* 986 * MOP_counter 987 * will be emit to five instructions in a row: 988 * adrp x1, :got:__profile_table + idx 989 * ldr w17, [x1,#:got_lo12:__profile_table] 990 * add w17, w17, #1 991 * str w17,[x1,,#:got_lo12:__profile_table] 992 */ 993DEFINE_MOP(MOP_counter, {&OpndDesc::Reg64ID,&OpndDesc::LiteralSrc},ISATOMIC|CANTHROW|ISINTRINSIC,kLtClinit,"intrinsic_counter","0,1", 4) 994 995/* 996 * will be emit to two instrunctions in a row: 997 * ldr wd, [xs] // xd and xs should be differenct register 998 * ldr wd, [xd] 999 */ 1000DEFINE_MOP(MOP_lazy_ldr, {&OpndDesc::Reg32ID,&OpndDesc::Reg64IS},ISATOMIC|CANTHROW|SPINTRINSIC|ISINTRINSIC,kLtClinitTail,"intrinsic_lazyload","0,1",2) 1001 1002/* 1003 * will be emit to three instrunctions in a row: 1004 * adrp xd, :got:__staticDecoupleValueOffset$$xxx+offset 1005 * ldr xd, [xd,#:got_lo12:__staticDecoupleValueOffset$$xx+offset] 1006 * ldr xzr, [xd] 1007 */ 1008DEFINE_MOP(MOP_lazy_ldr_static, {&OpndDesc::Reg64ID,&OpndDesc::LiteralSrc},ISATOMIC|CANTHROW|ISINTRINSIC,kLtAdrpLdr,"intrinsic_lazyloadstatic","0,1",3) 1009 1010/* A pseudo instruction followed MOP_lazy_ldr, to make sure xs and xd be allocated to different physical registers. */ 1011DEFINE_MOP(MOP_lazy_tail, {&OpndDesc::Reg32IS,&OpndDesc::Reg64IS},0,kLtUndef,"pseudo_lazy_tail","",0) 1012 1013DEFINE_MOP(MOP_adrp_ldr, {&OpndDesc::Reg64ID, &OpndDesc::LiteralSrc},ISATOMIC|CANTHROW|ISINTRINSIC,kLtAdrpLdr,"intrinsic_adrpldr","0,1",2) 1014 1015/* will be emit to two instructions in a row: 1016 * adrp xd, label 1017 * add xd, xd, #:lo12:label 1018 */ 1019DEFINE_MOP(MOP_adrp_label, {&OpndDesc::Reg64ID, &OpndDesc::Imm64},ISINTRINSIC,kLtAlu,"intrinsic_adrplabel","0,1", 2) 1020 1021/* 1022 * will be emit to three instrunctions in a row: 1023 * adrp xd, :got:__arrayClassCacheTable$$xxx+offset 1024 * ldr xd, [xd,#:got_lo12:__arrayClassCacheTable$$xx+offset] 1025 * ldr xzr, [xd] 1026 */ 1027DEFINE_MOP(MOP_arrayclass_cache_ldr, {&OpndDesc::Reg64ID,&OpndDesc::LiteralSrc},ISATOMIC|CANTHROW|ISINTRINSIC,kLtAdrpLdr,"intrinsic_loadarrayclass","0,1",3) 1028 1029/* 1030 * ldr x17, [xs,#112] 1031 * ldr wzr, [x17] 1032 */ 1033DEFINE_MOP(MOP_clinit_tail, {&OpndDesc::Reg64IS},ISATOMIC|CANTHROW|ISINTRINSIC,kLtClinitTail,"intrinsic_clinit_tail","0",2) 1034 1035/* 1036 * intrinsic Unsafe.getAndAddInt 1037 * intrinsic_get_add_int w0, xt, wt, ws, x1, x2, w3, label 1038 * add xt, x1, x2 1039 * label: 1040 * ldaxr w0, [xt] 1041 * add wt, w0, w3 1042 * stlxr ws, wt, [xt] 1043 * cbnz ws, label 1044 */ 1045DEFINE_MOP(MOP_get_and_addI, {&OpndDesc::Reg32ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_get_add_int","",5) 1046/* 1047 * intrinsic Unsafe.getAndAddLong 1048 * intrinsic_get_add_long x0, xt, xs, ws, x1, x2, x3, ws, label 1049 * add xt, x1, x2 1050 * label: 1051 * ldaxr x0, [xt] 1052 * add xs, x0, x3 1053 * stlxr ws, x2, [xt] 1054 * cbnz ws, label 1055 */ 1056DEFINE_MOP(MOP_get_and_addL, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_get_add_long","",5) 1057 1058/* 1059 * intrinsic Unsafe.getAndSetInt 1060 * intrinsic_get_set_int w0, xt, x1, x2, w3, label 1061 * add xt, x1, x2 1062 * label: 1063 * ldaxr w0, [xt] 1064 * stlxr w2, w3, [xt] 1065 * cbnz w2, label 1066 */ 1067DEFINE_MOP(MOP_get_and_setI, {&OpndDesc::Reg32ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_get_set_int","0,1,2,3,4",4) 1068/* 1069 * intrinsic Unsafe.getAndSetLong 1070 * intrinsic_get_set_long x0, x1, x2, x3, label 1071 * add xt, x1, x2 1072 * label: 1073 * ldaxr x0, [xt] 1074 * stlxr w2, x3, [xt] 1075 * cbnz w2, label 1076 */ 1077DEFINE_MOP(MOP_get_and_setL, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_get_set_long","0,1,2,3,4",4) 1078 1079/* 1080 * intrinsic Unsafe.compareAndSwapInt 1081 * intrinsic_compare_swap_int x0, xt, ws, x1, x2, w3, w4, lable1, label2 1082 * add xt, x1, x2 1083 * label1: 1084 * ldaxr ws, [xt] 1085 * cmp ws, w3 1086 * b.ne label2 1087 * stlxr ws, w4, [xt] 1088 * cbnz ws, label1 1089 * label2: 1090 * cset x0, eq 1091 */ 1092DEFINE_MOP(MOP_compare_and_swapI, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg32IS,&OpndDesc::Reg32IS,&OpndDesc::AddressName,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_compare_swap_int","0,1,2,3,4,5,6",7) 1093/* 1094 * intrinsic Unsafe.compareAndSwapLong 1095 * intrinsic_compare_swap_long x0, xt, xs, x1, x2, x3, x4, lable1, label2 1096 * add xt, x1, x2 1097 * label1: 1098 * ldaxr xs, [xt] 1099 * cmp xs, x3 1100 * b.ne label2 1101 * stlxr ws, x4, [xt] 1102 * cbnz ws, label1 1103 * label2: 1104 * cset x0, eq 1105 */ 1106DEFINE_MOP(MOP_compare_and_swapL, {&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::Reg64IS,&OpndDesc::AddressName,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_compare_swap_long","0,1,2,3,4,5,6",7) 1107 1108/* 1109 * intrinsic_string_indexof w0, x1, w2, x3, w4, x5, x6, x7, x8, x9, w10, Label.FIRST_LOOP, Label.STR2_NEXT, Label.STR1_LOOP, Label.STR1_NEXT, Label.LAST_WORD, Label.NOMATCH, Label.RET 1110 * cmp w4, w2 1111 * b.gt .Label.NOMATCH 1112 * sub w2, w2, w4 1113 * sub w4, w4, #8 1114 * mov w10, w2 1115 * uxtw x4, w4 1116 * uxtw x2, w2 1117 * add x3, x3, x4 1118 * add x1, x1, x2 1119 * neg x4, x4 1120 * neg x2, x2 1121 * ldr x5, [x3,x4] 1122 * .Label.FIRST_LOOP: 1123 * ldr x7, [x1,x2] 1124 * cmp x5, x7 1125 * b.eq .Label.STR1_LOOP 1126 * .Label.STR2_NEXT: 1127 * adds x2, x2, #1 1128 * b.le .Label.FIRST_LOOP 1129 * b .Label.NOMATCH 1130 * .Label.STR1_LOOP: 1131 * adds x8, x4, #8 1132 * add x9, x2, #8 1133 * b.ge .Label.LAST_WORD 1134 * .Label.STR1_NEXT: 1135 * ldr x6, [x3,x8] 1136 * ldr x7, [x1,x9] 1137 * cmp x6, x7 1138 * b.ne .Label.STR2_NEXT 1139 * adds x8, x8, #8 1140 * add x9, x9, #8 1141 * b.lt .Label.STR1_NEXT 1142 * .Label.LAST_WORD: 1143 * ldr x6, [x3] 1144 * sub x9, x1, x4 1145 * ldr x7, [x9,x2] 1146 * cmp x6, x7 1147 * b.ne .Label.STR2_NEXT 1148 * add w0, w10, w2 1149 * b .Label.RET 1150 * .Label.NOMATCH: 1151 * mov w0, #-1 1152 * .Label.RET: 1153 */ 1154DEFINE_MOP(MOP_string_indexof, {&OpndDesc::Reg32ID,&OpndDesc::Reg64IDS,&OpndDesc::Reg32IDS,&OpndDesc::Reg64IDS,&OpndDesc::Reg32IDS,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg64ID,&OpndDesc::Reg32ID,&OpndDesc::AddressName,&OpndDesc::AddressName,&OpndDesc::AddressName,&OpndDesc::AddressName,&OpndDesc::AddressName,&OpndDesc::AddressName,&OpndDesc::AddressName},HASLOOP|CANTHROW|SPINTRINSIC,kLtBranch,"intrinsic_string_indexof","0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17",36) 1155 1156/* MOP_tail_call_opt_xbl -- branch without link (call); this is a special definition */ 1157DEFINE_MOP(MOP_tail_call_opt_xbl, {&OpndDesc::AddressName,&OpndDesc::ListSrc},CANTHROW|ISTAILCALL,kLtBranch,"b","0", 1, kBranchImm,0x14000000) 1158/* MOP_tail_call_opt_xblr -- branch without link (call) to register; this is a special definition */ 1159DEFINE_MOP(MOP_tail_call_opt_xblr, {&OpndDesc::Reg64IS,&OpndDesc::ListSrc},CANTHROW|ISTAILCALL,kLtBranch,"br","0", 1, kBranchReg, 0xd61f0000) 1160 1161/* MOP_pseudo_param_def_x, */ 1162DEFINE_MOP(MOP_pseudo_param_def_x, {&OpndDesc::Reg64ID},0,kLtUndef,"//MOP_pseudo_param_def","0", 0) 1163 1164/* MOP_pseudo_param_def_w, */ 1165DEFINE_MOP(MOP_pseudo_param_def_w, {&OpndDesc::Reg32ID},0,kLtUndef,"//MOP_pseudo_param_def","0", 0) 1166 1167/* MOP_pseudo_param_def_d, */ 1168DEFINE_MOP(MOP_pseudo_param_def_d, {&OpndDesc::Reg64FD},0,kLtUndef,"//MOP_pseudo_param_def","0", 0) 1169 1170/* MOP_pseudo_param_def_s, */ 1171DEFINE_MOP(MOP_pseudo_param_def_s, {&OpndDesc::Reg32FD},0,kLtUndef,"//MOP_pseudo_param_def","0", 0) 1172 1173/* MOP_pseudo_param_store_x, */ 1174DEFINE_MOP(MOP_pseudo_param_store_x, {&OpndDesc::Mem64D},0,kLtUndef,"//MOP_pseudo_param_store_x","0", 0) 1175 1176/* MOP_pseudo_param_store_w, */ 1177DEFINE_MOP(MOP_pseudo_param_store_w, {&OpndDesc::Mem32D},0,kLtUndef,"//MOP_pseudo_param_store_w","0", 0) 1178 1179/* MOP_pseudo_ref_init_x, */ 1180DEFINE_MOP(MOP_pseudo_ref_init_x, {&OpndDesc::Mem64D},0,kLtUndef,"//MOP_pseudo_ref_init_x","0", 0) 1181 1182/* MOP_pseudo_ret_int, */ 1183DEFINE_MOP(MOP_pseudo_ret_int, {&OpndDesc::Reg64IS},0,kLtUndef,"//MOP_pseudo_ret_int","", 0) 1184 1185/* MOP_pseudo_ret_float, */ 1186DEFINE_MOP(MOP_pseudo_ret_float, {&OpndDesc::Reg64FS},0,kLtUndef,"//MOP_pseudo_ret_float","", 0) 1187 1188/* When exception occurs, R0 and R1 may be defined by runtime code. */ 1189/* MOP_pseudo_eh_def_x, */ 1190DEFINE_MOP(MOP_pseudo_eh_def_x, {&OpndDesc::Reg64ID},0,kLtUndef,"//MOP_pseudo_eh_def_x","0", 0) 1191 1192/* A pseudo instruction that used for seperating dependence graph. */ 1193/* MOP_pseudo_dependence_seperator, */ 1194DEFINE_MOP(MOP_pseudo_dependence_seperator, {},0,kLtUndef,"//MOP_pseudo_dependence_seperator","0", 0) 1195 1196/* A pseudo instruction that used for replacing MOP_clinit_tail after clinit merge in scheduling. */ 1197/* MOP_pseudo_none, */ 1198DEFINE_MOP(MOP_pseudo_none, {},0,kLtUndef,"//MOP_pseudo_none","0", 0) 1199 1200/* MOP_ret_assert_nonnull*/ 1201DEFINE_MOP(MOP_assert_nonnull, {&OpndDesc::Reg32ID,&OpndDesc::Mem32S},ISLOAD|CANTHROW|ISCALL,kLtUndef,"ldr","0,1",1,MOP_assert_nonnullValid,MOP_assert_nonnullSplit,kLoadStoreReg,0xb8400000) 1202 1203/*MOP_nop */ 1204DEFINE_MOP(MOP_nop, {},ISNOP,kLtAlu,"nop","", 1, kSystemInsn, 0xd503201f) 1205 1206/* phi node for SSA form */ 1207/* MOP_xphirr */ 1208DEFINE_MOP(MOP_xphirr, {&OpndDesc::Reg64ID,&OpndDesc::ListSrc},ISPHI,kLtAlu,"//phi","0,1",1) 1209/* MOP_wphirr */ 1210DEFINE_MOP(MOP_wphirr, {&OpndDesc::Reg32ID,&OpndDesc::ListSrc},ISPHI,kLtAlu,"//phi","0,1",1) 1211/* MOP_xvphis */ 1212DEFINE_MOP(MOP_xvphis, {&OpndDesc::Reg32FD,&OpndDesc::ListSrc},ISPHI,kLtFpalu,"//phi","0,1",1) 1213/* MOP_xvphid */ 1214DEFINE_MOP(MOP_xvphid, {&OpndDesc::Reg64FD,&OpndDesc::ListSrc},ISPHI,kLtFpalu,"//phi","0,1",1) 1215/* MOP_xvphivd */ 1216DEFINE_MOP(MOP_xvphivd, {&OpndDesc::Reg128VD,&OpndDesc::ListSrc},ISPHI,kLtFpalu,"movi","0,1",1) 1217 1218/* end of AArch64 instructions */ 1219