1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 #ifndef __HDMI_REG_CRG_H__ 19 #define __HDMI_REG_CRG_H__ 20 21 #include "hi_type.h" 22 23 typedef union { 24 struct { 25 unsigned int ssc_in_cken : 1; /* [0] */ 26 unsigned int ssc_bypass_cken : 1; /* [1] */ 27 unsigned int hdmitx_ctrl_osc_24m_cken : 1; /* [2] */ 28 unsigned int hdmitx_ctrl_cec_cken : 1; /* [3] */ 29 unsigned int hdmitx_ctrl_os_cken : 1; /* [4] */ 30 unsigned int hdmitx_ctrl_as_cken : 1; /* [5] */ 31 unsigned int hdmitx_ctrl_bus_srst_req : 1; /* [6] */ 32 unsigned int hdmitx_ctrl_srst_req : 1; /* [7] */ 33 unsigned int hdmitx_ctrl_cec_srst_req : 1; /* [8] */ 34 unsigned int hdmitx_ssc_srst_req : 1; /* [9] */ 35 unsigned int ssc_clk_div : 4; /* [13..10] */ 36 unsigned int reserved_0 : 2; /* [15..14] */ 37 unsigned int hdmitx_pxl_cken : 1; /* [16] */ 38 unsigned int reserved_1 : 2; /* [18..17] */ 39 unsigned int ssc_bypass_clk_sel : 1; /* [19] */ 40 } bits; 41 unsigned int u32; 42 } peri_crg67; 43 44 typedef union { 45 struct { 46 unsigned int phy_tmds_cken : 1; /* [0] */ 47 unsigned int reserved_0 : 3; /* [3..1] */ 48 unsigned int hdmitx_phy_srst_req : 1; /* [4] */ 49 unsigned int phy_tmds_srst_req : 1; /* [5] */ 50 unsigned int tmds_clk_div : 3; /* [8..6] */ 51 unsigned int reserved_1 : 23; /* [31..9] */ 52 } bits; 53 unsigned int u32; 54 } peri_crg69; 55 56 typedef struct { 57 volatile peri_crg67 crg68; /* 0x110 */ 58 volatile peri_crg69 crg69; /* 0x114 */ 59 } hdmi_reg_crg; 60 61 int hdmi_reg_crg_init(void); 62 int hdmi_reg_crg_deinit(void); 63 int hdmi_reg_ssc_in_cken_set(unsigned int ssc_in_cken); 64 int hdmi_reg_ssc_bypass_cken_set(unsigned int ssc_bypass_cken); 65 int hdmi_reg_ctrl_osc_24m_cken_set(unsigned int hdmitx_ctrl_osc_24m_cken); 66 int hdmi_reg_ctrl_cec_cken_set(unsigned int hdmitx_ctrl_cec_cken); 67 int hdmi_reg_ctrl_os_cken_set(unsigned int hdmitx_ctrl_os_cken); 68 int hdmi_reg_ctrl_as_cken_set(unsigned int hdmitx_ctrl_as_cken); 69 int hdmi_reg_ctrl_bus_srst_req_set(unsigned int hdmitx_ctrl_bus_srst_req); 70 int hdmi_reg_ctrl_srst_req_set(unsigned int hdmitx_ctrl_srst_req); 71 int hdmi_reg_ctrl_cec_srst_req_set(unsigned int hdmitx_ctrl_cec_srst_req); 72 int hdmi_reg_ssc_srst_req_set(unsigned int hdmitx_ssc_srst_req); 73 int hdmi_reg_ssc_clk_div_set(unsigned int ssc_clk_div); 74 int hdmi_reg_pxl_cken_set(unsigned int hdmitx_pxl_cken); 75 int hdmi_reg_hdmirx_phy_tmds_cken_set(unsigned int phy_tmds_cken); 76 int hdmi_reg_phy_srst_req_set(unsigned int hdmitx_phy_srst_req); 77 int hdmi_reg_phy_srst_req_get(hi_void); 78 int hdmi_reg_phy_tmds_srst_req_set(unsigned int phy_tmds_srst_req); 79 int hdmi_reg_phy_tmds_srst_req_get(hi_void); 80 int hdmi_reg_phy_srst_req_get(hi_void); 81 int hdmi_reg_tmds_clk_div_set(unsigned int tmds_clk_div); 82 83 #endif /* __HDMI_REG_CRG_H__ */ 84 85