1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SDIO Host Controller Spec header file 4 * Register map and definitions for the Standard Host Controller 5 * 6 * Copyright (C) 1999-2019, Broadcom. 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sdioh.h 768099 2018-06-18 13:58:07Z $ 30 */ 31 32 #ifndef _SDIOH_H 33 #define _SDIOH_H 34 35 #define SD_SysAddr 0x000 36 #define SD_BlockSize 0x004 37 #define SD_BlockCount 0x006 38 #define SD_Arg0 0x008 39 #define SD_Arg1 0x00A 40 #define SD_TransferMode 0x00C 41 #define SD_Command 0x00E 42 #define SD_Response0 0x010 43 #define SD_Response1 0x012 44 #define SD_Response2 0x014 45 #define SD_Response3 0x016 46 #define SD_Response4 0x018 47 #define SD_Response5 0x01A 48 #define SD_Response6 0x01C 49 #define SD_Response7 0x01E 50 #define SD_BufferDataPort0 0x020 51 #define SD_BufferDataPort1 0x022 52 #define SD_PresentState 0x024 53 #define SD_HostCntrl 0x028 54 #define SD_PwrCntrl 0x029 55 #define SD_BlockGapCntrl 0x02A 56 #define SD_WakeupCntrl 0x02B 57 #define SD_ClockCntrl 0x02C 58 #define SD_TimeoutCntrl 0x02E 59 #define SD_SoftwareReset 0x02F 60 #define SD_IntrStatus 0x030 61 #define SD_ErrorIntrStatus 0x032 62 #define SD_IntrStatusEnable 0x034 63 #define SD_ErrorIntrStatusEnable 0x036 64 #define SD_IntrSignalEnable 0x038 65 #define SD_ErrorIntrSignalEnable 0x03A 66 #define SD_CMD12ErrorStatus 0x03C 67 #define SD_Capabilities 0x040 68 #define SD_Capabilities3 0x044 69 #define SD_MaxCurCap 0x048 70 #define SD_MaxCurCap_Reserved 0x04C 71 #define SD_ADMA_ErrStatus 0x054 72 #define SD_ADMA_SysAddr 0x58 73 #define SD_SlotInterruptStatus 0x0FC 74 #define SD_HostControllerVersion 0x0FE 75 #define SD_GPIO_Reg 0x100 76 #define SD_GPIO_OE 0x104 77 #define SD_GPIO_Enable 0x108 78 79 /* SD specific registers in PCI config space */ 80 #define SD_SlotInfo 0x40 81 82 /* HC 3.0 specific registers and offsets */ 83 #define SD3_HostCntrl2 0x03E 84 /* preset regsstart and count */ 85 #define SD3_PresetValStart 0x060 86 #define SD3_PresetValCount 8 87 /* preset-indiv regs */ 88 #define SD3_PresetVal_init 0x060 89 #define SD3_PresetVal_default 0x062 90 #define SD3_PresetVal_HS 0x064 91 #define SD3_PresetVal_SDR12 0x066 92 #define SD3_PresetVal_SDR25 0x068 93 #define SD3_PresetVal_SDR50 0x06a 94 #define SD3_PresetVal_SDR104 0x06c 95 #define SD3_PresetVal_DDR50 0x06e 96 /* SDIO3.0 Revx specific Registers */ 97 #define SD3_Tuning_Info_Register 0x0EC 98 #define SD3_WL_BT_reset_register 0x0F0 99 100 /* preset value indices */ 101 #define SD3_PRESETVAL_INITIAL_IX 0 102 #define SD3_PRESETVAL_DESPEED_IX 1 103 #define SD3_PRESETVAL_HISPEED_IX 2 104 #define SD3_PRESETVAL_SDR12_IX 3 105 #define SD3_PRESETVAL_SDR25_IX 4 106 #define SD3_PRESETVAL_SDR50_IX 5 107 #define SD3_PRESETVAL_SDR104_IX 6 108 #define SD3_PRESETVAL_DDR50_IX 7 109 110 /* SD_Capabilities reg (0x040) */ 111 #define CAP_TO_CLKFREQ_M BITFIELD_MASK(6) 112 #define CAP_TO_CLKFREQ_S 0 113 #define CAP_TO_CLKUNIT_M BITFIELD_MASK(1) 114 #define CAP_TO_CLKUNIT_S 7 115 /* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2 116 bits are reserved. going ahead with 8 bits, as it is req for 3.0 117 */ 118 #define CAP_BASECLK_M BITFIELD_MASK(8) 119 #define CAP_BASECLK_S 8 120 #define CAP_MAXBLOCK_M BITFIELD_MASK(2) 121 #define CAP_MAXBLOCK_S 16 122 #define CAP_ADMA2_M BITFIELD_MASK(1) 123 #define CAP_ADMA2_S 19 124 #define CAP_ADMA1_M BITFIELD_MASK(1) 125 #define CAP_ADMA1_S 20 126 #define CAP_HIGHSPEED_M BITFIELD_MASK(1) 127 #define CAP_HIGHSPEED_S 21 128 #define CAP_DMA_M BITFIELD_MASK(1) 129 #define CAP_DMA_S 22 130 #define CAP_SUSPEND_M BITFIELD_MASK(1) 131 #define CAP_SUSPEND_S 23 132 #define CAP_VOLT_3_3_M BITFIELD_MASK(1) 133 #define CAP_VOLT_3_3_S 24 134 #define CAP_VOLT_3_0_M BITFIELD_MASK(1) 135 #define CAP_VOLT_3_0_S 25 136 #define CAP_VOLT_1_8_M BITFIELD_MASK(1) 137 #define CAP_VOLT_1_8_S 26 138 #define CAP_64BIT_HOST_M BITFIELD_MASK(1) 139 #define CAP_64BIT_HOST_S 28 140 141 #define SDIO_OCR_READ_FAIL (2) 142 143 #define CAP_ASYNCINT_SUP_M BITFIELD_MASK(1) 144 #define CAP_ASYNCINT_SUP_S 29 145 146 #define CAP_SLOTTYPE_M BITFIELD_MASK(2) 147 #define CAP_SLOTTYPE_S 30 148 149 #define CAP3_MSBits_OFFSET (32) 150 /* note: following are caps MSB32 bits. 151 So the bits start from 0, instead of 32. that is why 152 CAP3_MSBits_OFFSET is subtracted. 153 */ 154 #define CAP3_SDR50_SUP_M BITFIELD_MASK(1) 155 #define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET) 156 157 #define CAP3_SDR104_SUP_M BITFIELD_MASK(1) 158 #define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET) 159 160 #define CAP3_DDR50_SUP_M BITFIELD_MASK(1) 161 #define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET) 162 163 /* for knowing the clk caps in a single read */ 164 #define CAP3_30CLKCAP_M BITFIELD_MASK(3) 165 #define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET) 166 167 #define CAP3_DRIVTYPE_A_M BITFIELD_MASK(1) 168 #define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET) 169 170 #define CAP3_DRIVTYPE_C_M BITFIELD_MASK(1) 171 #define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET) 172 173 #define CAP3_DRIVTYPE_D_M BITFIELD_MASK(1) 174 #define CAP3_DRIVTYPE_D_S (38 - CAP3_MSBits_OFFSET) 175 176 #define CAP3_RETUNING_TC_M BITFIELD_MASK(4) 177 #define CAP3_RETUNING_TC_S (40 - CAP3_MSBits_OFFSET) 178 179 #define CAP3_TUNING_SDR50_M BITFIELD_MASK(1) 180 #define CAP3_TUNING_SDR50_S (45 - CAP3_MSBits_OFFSET) 181 182 #define CAP3_RETUNING_MODES_M BITFIELD_MASK(2) 183 #define CAP3_RETUNING_MODES_S (46 - CAP3_MSBits_OFFSET) 184 185 #define CAP3_RETUNING_TC_DISABLED (0x0) 186 #define CAP3_RETUNING_TC_1024S (0xB) 187 #define CAP3_RETUNING_TC_OTHER (0xF) 188 189 #define CAP3_CLK_MULT_M BITFIELD_MASK(8) 190 #define CAP3_CLK_MULT_S (48 - CAP3_MSBits_OFFSET) 191 192 #define PRESET_DRIVR_SELECT_M BITFIELD_MASK(2) 193 #define PRESET_DRIVR_SELECT_S 14 194 195 #define PRESET_CLK_DIV_M BITFIELD_MASK(10) 196 #define PRESET_CLK_DIV_S 0 197 198 /* SD_MaxCurCap reg (0x048) */ 199 #define CAP_CURR_3_3_M BITFIELD_MASK(8) 200 #define CAP_CURR_3_3_S 0 201 #define CAP_CURR_3_0_M BITFIELD_MASK(8) 202 #define CAP_CURR_3_0_S 8 203 #define CAP_CURR_1_8_M BITFIELD_MASK(8) 204 #define CAP_CURR_1_8_S 16 205 206 /* SD_SysAddr: Offset 0x0000, Size 4 bytes */ 207 208 /* SD_BlockSize: Offset 0x004, Size 2 bytes */ 209 #define BLKSZ_BLKSZ_M BITFIELD_MASK(12) 210 #define BLKSZ_BLKSZ_S 0 211 #define BLKSZ_BNDRY_M BITFIELD_MASK(3) 212 #define BLKSZ_BNDRY_S 12 213 214 /* SD_BlockCount: Offset 0x006, size 2 bytes */ 215 216 /* SD_Arg0: Offset 0x008, size = 4 bytes */ 217 /* SD_TransferMode Offset 0x00C, size = 2 bytes */ 218 #define XFER_DMA_ENABLE_M BITFIELD_MASK(1) 219 #define XFER_DMA_ENABLE_S 0 220 #define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1) 221 #define XFER_BLK_COUNT_EN_S 1 222 #define XFER_CMD_12_EN_M BITFIELD_MASK(1) 223 #define XFER_CMD_12_EN_S 2 224 #define XFER_DATA_DIRECTION_M BITFIELD_MASK(1) 225 #define XFER_DATA_DIRECTION_S 4 226 #define XFER_MULTI_BLOCK_M BITFIELD_MASK(1) 227 #define XFER_MULTI_BLOCK_S 5 228 229 /* SD_Command: Offset 0x00E, size = 2 bytes */ 230 /* resp_type field */ 231 #define RESP_TYPE_NONE 0 232 #define RESP_TYPE_136 1 233 #define RESP_TYPE_48 2 234 #define RESP_TYPE_48_BUSY 3 235 /* type field */ 236 #define CMD_TYPE_NORMAL 0 237 #define CMD_TYPE_SUSPEND 1 238 #define CMD_TYPE_RESUME 2 239 #define CMD_TYPE_ABORT 3 240 241 #define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */ 242 #define CMD_RESP_TYPE_S 0 243 #define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */ 244 #define CMD_CRC_EN_S 3 245 #define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */ 246 #define CMD_INDEX_EN_S 4 247 #define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */ 248 #define CMD_DATA_EN_S 5 249 #define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc 250 */ 251 #define CMD_TYPE_S 6 252 #define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */ 253 #define CMD_INDEX_S 8 254 255 /* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */ 256 /* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */ 257 /* SD_PresentState : Offset 0x024, size = 4 bytes */ 258 #define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */ 259 #define PRES_CMD_INHIBIT_S 0 260 #define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */ 261 #define PRES_DAT_INHIBIT_S 1 262 #define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */ 263 #define PRES_DAT_BUSY_S 2 264 #define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */ 265 #define PRES_PRESENT_RSVD_S 3 266 #define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */ 267 #define PRES_WRITE_ACTIVE_S 8 268 #define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */ 269 #define PRES_READ_ACTIVE_S 9 270 #define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */ 271 #define PRES_WRITE_DATA_RDY_S 10 272 #define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */ 273 #define PRES_READ_DATA_RDY_S 11 274 #define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */ 275 #define PRES_CARD_PRESENT_S 16 276 #define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */ 277 #define PRES_CARD_STABLE_S 17 278 #define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */ 279 #define PRES_CARD_PRESENT_RAW_S 18 280 #define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */ 281 #define PRES_WRITE_ENABLED_S 19 282 #define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */ 283 #define PRES_DAT_SIGNAL_S 20 284 #define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */ 285 #define PRES_CMD_SIGNAL_S 24 286 287 /* SD_HostCntrl: Offset 0x028, size = 1 bytes */ 288 #define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */ 289 #define HOST_LED_S 0 290 #define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */ 291 #define HOST_DATA_WIDTH_S 1 292 #define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */ 293 #define HOST_DMA_SEL_S 3 294 #define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */ 295 #define HOST_HI_SPEED_EN_S 2 296 297 /* Host Control2: */ 298 #define HOSTCtrl2_PRESVAL_EN_M BITFIELD_MASK(1) /* 1 bit */ 299 #define HOSTCtrl2_PRESVAL_EN_S 15 /* bit# */ 300 301 #define HOSTCtrl2_ASYINT_EN_M BITFIELD_MASK(1) /* 1 bit */ 302 #define HOSTCtrl2_ASYINT_EN_S 14 /* bit# */ 303 304 #define HOSTCtrl2_SAMPCLK_SEL_M BITFIELD_MASK(1) /* 1 bit */ 305 #define HOSTCtrl2_SAMPCLK_SEL_S 7 /* bit# */ 306 307 #define HOSTCtrl2_EXEC_TUNING_M BITFIELD_MASK(1) /* 1 bit */ 308 #define HOSTCtrl2_EXEC_TUNING_S 6 /* bit# */ 309 310 #define HOSTCtrl2_DRIVSTRENGTH_SEL_M BITFIELD_MASK(2) /* 2 bit */ 311 #define HOSTCtrl2_DRIVSTRENGTH_SEL_S 4 /* bit# */ 312 313 #define HOSTCtrl2_1_8SIG_EN_M BITFIELD_MASK(1) /* 1 bit */ 314 #define HOSTCtrl2_1_8SIG_EN_S 3 /* bit# */ 315 316 #define HOSTCtrl2_UHSMODE_SEL_M BITFIELD_MASK(3) /* 3 bit */ 317 #define HOSTCtrl2_UHSMODE_SEL_S 0 /* bit# */ 318 319 #define HOST_CONTR_VER_2 (1) 320 #define HOST_CONTR_VER_3 (2) 321 322 /* misc defines */ 323 #define SD1_MODE 0x1 /* SD Host Cntrlr Spec */ 324 #define SD4_MODE 0x2 /* SD Host Cntrlr Spec */ 325 326 /* SD_PwrCntrl: Offset 0x029, size = 1 bytes */ 327 #define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */ 328 #define PWR_BUS_EN_S 0 329 #define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */ 330 #define PWR_VOLTS_S 1 331 332 /* SD_SoftwareReset: Offset 0x02F, size = 1 byte */ 333 #define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */ 334 #define SW_RESET_ALL_S 0 335 #define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */ 336 #define SW_RESET_CMD_S 1 337 #define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */ 338 #define SW_RESET_DAT_S 2 339 340 /* SD_IntrStatus: Offset 0x030, size = 2 bytes */ 341 /* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */ 342 #define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */ 343 #define INTSTAT_CMD_COMPLETE_S 0 344 #define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1) 345 #define INTSTAT_XFER_COMPLETE_S 1 346 #define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1) 347 #define INTSTAT_BLOCK_GAP_EVENT_S 2 348 #define INTSTAT_DMA_INT_M BITFIELD_MASK(1) 349 #define INTSTAT_DMA_INT_S 3 350 #define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1) 351 #define INTSTAT_BUF_WRITE_READY_S 4 352 #define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1) 353 #define INTSTAT_BUF_READ_READY_S 5 354 #define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1) 355 #define INTSTAT_CARD_INSERTION_S 6 356 #define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1) 357 #define INTSTAT_CARD_REMOVAL_S 7 358 #define INTSTAT_CARD_INT_M BITFIELD_MASK(1) 359 #define INTSTAT_CARD_INT_S 8 360 #define INTSTAT_RETUNING_INT_M BITFIELD_MASK(1) /* Bit 12 */ 361 #define INTSTAT_RETUNING_INT_S 12 362 #define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */ 363 #define INTSTAT_ERROR_INT_S 15 364 365 /* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */ 366 /* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */ 367 #define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1) 368 #define ERRINT_CMD_TIMEOUT_S 0 369 #define ERRINT_CMD_CRC_M BITFIELD_MASK(1) 370 #define ERRINT_CMD_CRC_S 1 371 #define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1) 372 #define ERRINT_CMD_ENDBIT_S 2 373 #define ERRINT_CMD_INDEX_M BITFIELD_MASK(1) 374 #define ERRINT_CMD_INDEX_S 3 375 #define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1) 376 #define ERRINT_DATA_TIMEOUT_S 4 377 #define ERRINT_DATA_CRC_M BITFIELD_MASK(1) 378 #define ERRINT_DATA_CRC_S 5 379 #define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1) 380 #define ERRINT_DATA_ENDBIT_S 6 381 #define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1) 382 #define ERRINT_CURRENT_LIMIT_S 7 383 #define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1) 384 #define ERRINT_AUTO_CMD12_S 8 385 #define ERRINT_VENDOR_M BITFIELD_MASK(4) 386 #define ERRINT_VENDOR_S 12 387 #define ERRINT_ADMA_M BITFIELD_MASK(1) 388 #define ERRINT_ADMA_S 9 389 390 /* Also provide definitions in "normal" form to allow combined masks */ 391 #define ERRINT_CMD_TIMEOUT_BIT 0x0001 392 #define ERRINT_CMD_CRC_BIT 0x0002 393 #define ERRINT_CMD_ENDBIT_BIT 0x0004 394 #define ERRINT_CMD_INDEX_BIT 0x0008 395 #define ERRINT_DATA_TIMEOUT_BIT 0x0010 396 #define ERRINT_DATA_CRC_BIT 0x0020 397 #define ERRINT_DATA_ENDBIT_BIT 0x0040 398 #define ERRINT_CURRENT_LIMIT_BIT 0x0080 399 #define ERRINT_AUTO_CMD12_BIT 0x0100 400 #define ERRINT_ADMA_BIT 0x0200 401 402 /* Masks to select CMD vs. DATA errors */ 403 #define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\ 404 ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT) 405 #define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\ 406 ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT) 407 #define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS) 408 409 /* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */ 410 /* SD_ClockCntrl : Offset 0x02C , size = bytes */ 411 /* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */ 412 /* SD_IntrStatus : Offset 0x030 , size = bytes */ 413 /* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */ 414 /* SD_IntrStatusEnable : Offset 0x034 , size = bytes */ 415 /* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */ 416 /* SD_IntrSignalEnable : Offset 0x038 , size = bytes */ 417 /* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */ 418 /* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */ 419 /* SD_Capabilities : Offset 0x040 , size = bytes */ 420 /* SD_MaxCurCap : Offset 0x048 , size = bytes */ 421 /* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */ 422 /* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */ 423 /* SD_HostControllerVersion : Offset 0x0FE , size = bytes */ 424 425 /* SDIO Host Control Register DMA Mode Definitions */ 426 #define SDIOH_SDMA_MODE 0 427 #define SDIOH_ADMA1_MODE 1 428 #define SDIOH_ADMA2_MODE 2 429 #define SDIOH_ADMA2_64_MODE 3 430 431 #define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */ 432 #define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */ 433 #define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */ 434 #define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */ 435 #define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */ 436 #define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */ 437 #define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */ 438 #define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */ 439 440 /* ADMA2 Descriptor Table Entry for 32-bit Address */ 441 typedef struct adma2_dscr_32b { 442 uint32 len_attr; 443 uint32 phys_addr; 444 } adma2_dscr_32b_t; 445 446 /* ADMA1 Descriptor Table Entry */ 447 typedef struct adma1_dscr { 448 uint32 phys_addr_attr; 449 } adma1_dscr_t; 450 451 #endif /* _SDIOH_H */ 452