Searched refs:vsync_source (Results 1 – 8 of 8) sorted by relevance
140 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && in dpu_hw_setup_vsync_source()141 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { in dpu_hw_setup_vsync_source()142 switch (cfg->vsync_source) { in dpu_hw_setup_vsync_source()205 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_source_and_vsync_sel()
67 u32 vsync_source; member
108 void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
460 u32 vsync_source) in dpu_hw_intf_vsync_sel() argument469 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); in dpu_hw_intf_vsync_sel()
719 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; in _dpu_encoder_update_vsync_source()721 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; in _dpu_encoder_update_vsync_source()730 vsync_cfg.vsync_source); in _dpu_encoder_update_vsync_source()
173 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_source()177 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && in dpu_hw_setup_vsync_source()178 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { in dpu_hw_setup_vsync_source()179 switch (cfg->vsync_source) { in dpu_hw_setup_vsync_source()
68 u32 vsync_source; member
687 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; in _dpu_encoder_update_vsync_source()689 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; in _dpu_encoder_update_vsync_source()