1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Broadcom GENET MDIO routines
4 *
5 * Copyright (c) 2014-2017 Broadcom
6 */
7
8 #include <linux/acpi.h>
9 #include <linux/types.h>
10 #include <linux/delay.h>
11 #include <linux/wait.h>
12 #include <linux/mii.h>
13 #include <linux/ethtool.h>
14 #include <linux/bitops.h>
15 #include <linux/netdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/brcmphy.h>
20 #include <linux/of.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/platform_data/bcmgenet.h>
24 #include <linux/platform_data/mdio-bcm-unimac.h>
25
26 #include "bcmgenet.h"
27
28 /* setup netdev link state when PHY link status change and
29 * update UMAC and RGMII block when link up
30 */
bcmgenet_mii_setup(struct net_device * dev)31 void bcmgenet_mii_setup(struct net_device *dev)
32 {
33 struct bcmgenet_priv *priv = netdev_priv(dev);
34 struct phy_device *phydev = dev->phydev;
35 u32 reg, cmd_bits = 0;
36 bool status_changed = false;
37
38 if (priv->old_link != phydev->link) {
39 status_changed = true;
40 priv->old_link = phydev->link;
41 }
42
43 if (phydev->link) {
44 /* check speed/duplex/pause changes */
45 if (priv->old_speed != phydev->speed) {
46 status_changed = true;
47 priv->old_speed = phydev->speed;
48 }
49
50 if (priv->old_duplex != phydev->duplex) {
51 status_changed = true;
52 priv->old_duplex = phydev->duplex;
53 }
54
55 if (priv->old_pause != phydev->pause) {
56 status_changed = true;
57 priv->old_pause = phydev->pause;
58 }
59
60 /* done if nothing has changed */
61 if (!status_changed)
62 return;
63
64 /* speed */
65 if (phydev->speed == SPEED_1000)
66 cmd_bits = UMAC_SPEED_1000;
67 else if (phydev->speed == SPEED_100)
68 cmd_bits = UMAC_SPEED_100;
69 else
70 cmd_bits = UMAC_SPEED_10;
71 cmd_bits <<= CMD_SPEED_SHIFT;
72
73 /* duplex */
74 if (phydev->duplex != DUPLEX_FULL)
75 cmd_bits |= CMD_HD_EN;
76
77 /* pause capability */
78 if (!phydev->pause)
79 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
80
81 /*
82 * Program UMAC and RGMII block based on established
83 * link speed, duplex, and pause. The speed set in
84 * umac->cmd tell RGMII block which clock to use for
85 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
86 * Receive clock is provided by the PHY.
87 */
88 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
89 reg &= ~OOB_DISABLE;
90 reg |= RGMII_LINK;
91 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
92
93 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
94 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
95 CMD_HD_EN |
96 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
97 reg |= cmd_bits;
98 if (reg & CMD_SW_RESET) {
99 reg &= ~CMD_SW_RESET;
100 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
101 udelay(2);
102 reg |= CMD_TX_EN | CMD_RX_EN;
103 }
104 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
105 } else {
106 /* done if nothing has changed */
107 if (!status_changed)
108 return;
109
110 /* needed for MoCA fixed PHY to reflect correct link status */
111 netif_carrier_off(dev);
112 }
113
114 phy_print_status(phydev);
115 }
116
117
bcmgenet_fixed_phy_link_update(struct net_device * dev,struct fixed_phy_status * status)118 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
119 struct fixed_phy_status *status)
120 {
121 struct bcmgenet_priv *priv;
122 u32 reg;
123
124 if (dev && dev->phydev && status) {
125 priv = netdev_priv(dev);
126 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
127 status->link = !!(reg & MODE_LINK_STATUS);
128 }
129
130 return 0;
131 }
132
bcmgenet_phy_power_set(struct net_device * dev,bool enable)133 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
134 {
135 struct bcmgenet_priv *priv = netdev_priv(dev);
136 u32 reg = 0;
137
138 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
139 if (GENET_IS_V4(priv)) {
140 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
141 if (enable) {
142 reg &= ~EXT_CK25_DIS;
143 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
144 mdelay(1);
145
146 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
147 reg |= EXT_GPHY_RESET;
148 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
149 mdelay(1);
150
151 reg &= ~EXT_GPHY_RESET;
152 } else {
153 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
154 EXT_GPHY_RESET;
155 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
156 mdelay(1);
157 reg |= EXT_CK25_DIS;
158 }
159 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
160 udelay(60);
161 } else {
162 mdelay(1);
163 }
164 }
165
bcmgenet_moca_phy_setup(struct bcmgenet_priv * priv)166 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
167 {
168 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
169 fixed_phy_set_link_update(priv->dev->phydev,
170 bcmgenet_fixed_phy_link_update);
171 }
172
bcmgenet_mii_config(struct net_device * dev,bool init)173 int bcmgenet_mii_config(struct net_device *dev, bool init)
174 {
175 struct bcmgenet_priv *priv = netdev_priv(dev);
176 struct phy_device *phydev = dev->phydev;
177 struct device *kdev = &priv->pdev->dev;
178 const char *phy_name = NULL;
179 u32 id_mode_dis = 0;
180 u32 port_ctrl;
181 u32 reg;
182
183 switch (priv->phy_interface) {
184 case PHY_INTERFACE_MODE_INTERNAL:
185 phy_name = "internal PHY";
186 fallthrough;
187 case PHY_INTERFACE_MODE_MOCA:
188 /* Irrespective of the actually configured PHY speed (100 or
189 * 1000) GENETv4 only has an internal GPHY so we will just end
190 * up masking the Gigabit features from what we support, not
191 * switching to the EPHY
192 */
193 if (GENET_IS_V4(priv))
194 port_ctrl = PORT_MODE_INT_GPHY;
195 else
196 port_ctrl = PORT_MODE_INT_EPHY;
197
198 if (!phy_name) {
199 phy_name = "MoCA";
200 if (!GENET_IS_V5(priv))
201 port_ctrl |= LED_ACT_SOURCE_MAC;
202 bcmgenet_moca_phy_setup(priv);
203 }
204 break;
205
206 case PHY_INTERFACE_MODE_MII:
207 phy_name = "external MII";
208 phy_set_max_speed(phydev, SPEED_100);
209 port_ctrl = PORT_MODE_EXT_EPHY;
210 break;
211
212 case PHY_INTERFACE_MODE_REVMII:
213 phy_name = "external RvMII";
214 /* of_mdiobus_register took care of reading the 'max-speed'
215 * PHY property for us, effectively limiting the PHY supported
216 * capabilities, use that knowledge to also configure the
217 * Reverse MII interface correctly.
218 */
219 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
220 dev->phydev->supported))
221 port_ctrl = PORT_MODE_EXT_RVMII_50;
222 else
223 port_ctrl = PORT_MODE_EXT_RVMII_25;
224 break;
225
226 case PHY_INTERFACE_MODE_RGMII:
227 /* RGMII_NO_ID: TXC transitions at the same time as TXD
228 * (requires PCB or receiver-side delay)
229 *
230 * ID is implicitly disabled for 100Mbps (RG)MII operation.
231 */
232 phy_name = "external RGMII (no delay)";
233 id_mode_dis = BIT(16);
234 port_ctrl = PORT_MODE_EXT_GPHY;
235 break;
236
237 case PHY_INTERFACE_MODE_RGMII_TXID:
238 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */
239 phy_name = "external RGMII (TX delay)";
240 port_ctrl = PORT_MODE_EXT_GPHY;
241 break;
242
243 case PHY_INTERFACE_MODE_RGMII_RXID:
244 phy_name = "external RGMII (RX delay)";
245 port_ctrl = PORT_MODE_EXT_GPHY;
246 break;
247 default:
248 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
249 return -EINVAL;
250 }
251
252 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
253
254 priv->ext_phy = !priv->internal_phy &&
255 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
256
257 /* This is an external PHY (xMII), so we need to enable the RGMII
258 * block for the interface to work
259 */
260 if (priv->ext_phy) {
261 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
262 reg &= ~ID_MODE_DIS;
263 reg |= id_mode_dis;
264 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
265 reg |= RGMII_MODE_EN_V123;
266 else
267 reg |= RGMII_MODE_EN;
268 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
269 }
270
271 if (init)
272 dev_info(kdev, "configuring instance for %s\n", phy_name);
273
274 return 0;
275 }
276
bcmgenet_mii_probe(struct net_device * dev)277 int bcmgenet_mii_probe(struct net_device *dev)
278 {
279 struct bcmgenet_priv *priv = netdev_priv(dev);
280 struct device *kdev = &priv->pdev->dev;
281 struct device_node *dn = kdev->of_node;
282 struct phy_device *phydev;
283 u32 phy_flags = 0;
284 int ret;
285
286 /* Communicate the integrated PHY revision */
287 if (priv->internal_phy)
288 phy_flags = priv->gphy_rev;
289
290 /* Initialize link state variables that bcmgenet_mii_setup() uses */
291 priv->old_link = -1;
292 priv->old_speed = -1;
293 priv->old_duplex = -1;
294 priv->old_pause = -1;
295
296 if (dn) {
297 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
298 phy_flags, priv->phy_interface);
299 if (!phydev) {
300 pr_err("could not attach to PHY\n");
301 return -ENODEV;
302 }
303 } else {
304 if (has_acpi_companion(kdev)) {
305 char mdio_bus_id[MII_BUS_ID_SIZE];
306 struct mii_bus *unimacbus;
307
308 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
309 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
310
311 unimacbus = mdio_find_bus(mdio_bus_id);
312 if (!unimacbus) {
313 pr_err("Unable to find mii\n");
314 return -ENODEV;
315 }
316 phydev = phy_find_first(unimacbus);
317 put_device(&unimacbus->dev);
318 if (!phydev) {
319 pr_err("Unable to find PHY\n");
320 return -ENODEV;
321 }
322 } else {
323 phydev = dev->phydev;
324 }
325 phydev->dev_flags = phy_flags;
326
327 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
328 priv->phy_interface);
329 if (ret) {
330 pr_err("could not attach to PHY\n");
331 return -ENODEV;
332 }
333 }
334
335 /* Configure port multiplexer based on what the probed PHY device since
336 * reading the 'max-speed' property determines the maximum supported
337 * PHY speed which is needed for bcmgenet_mii_config() to configure
338 * things appropriately.
339 */
340 ret = bcmgenet_mii_config(dev, true);
341 if (ret) {
342 phy_disconnect(dev->phydev);
343 return ret;
344 }
345
346 linkmode_copy(phydev->advertising, phydev->supported);
347
348 /* The internal PHY has its link interrupts routed to the
349 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
350 * that prevents the signaling of link UP interrupts when
351 * the link operates at 10Mbps, so fallback to polling for
352 * those versions of GENET.
353 */
354 if (priv->internal_phy && !GENET_IS_V5(priv))
355 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
356
357 return 0;
358 }
359
bcmgenet_mii_of_find_mdio(struct bcmgenet_priv * priv)360 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
361 {
362 struct device_node *dn = priv->pdev->dev.of_node;
363 struct device *kdev = &priv->pdev->dev;
364 char *compat;
365
366 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
367 if (!compat)
368 return NULL;
369
370 priv->mdio_dn = of_get_compatible_child(dn, compat);
371 kfree(compat);
372 if (!priv->mdio_dn) {
373 dev_err(kdev, "unable to find MDIO bus node\n");
374 return NULL;
375 }
376
377 return priv->mdio_dn;
378 }
379
bcmgenet_mii_pdata_init(struct bcmgenet_priv * priv,struct unimac_mdio_pdata * ppd)380 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
381 struct unimac_mdio_pdata *ppd)
382 {
383 struct device *kdev = &priv->pdev->dev;
384 struct bcmgenet_platform_data *pd = kdev->platform_data;
385
386 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
387 /*
388 * Internal or external PHY with MDIO access
389 */
390 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
391 ppd->phy_mask = 1 << pd->phy_address;
392 else
393 ppd->phy_mask = 0;
394 }
395 }
396
bcmgenet_mii_wait(void * wait_func_data)397 static int bcmgenet_mii_wait(void *wait_func_data)
398 {
399 struct bcmgenet_priv *priv = wait_func_data;
400
401 wait_event_timeout(priv->wq,
402 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
403 & MDIO_START_BUSY),
404 HZ / 100);
405 return 0;
406 }
407
bcmgenet_mii_register(struct bcmgenet_priv * priv)408 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
409 {
410 struct platform_device *pdev = priv->pdev;
411 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
412 struct device_node *dn = pdev->dev.of_node;
413 struct unimac_mdio_pdata ppd;
414 struct platform_device *ppdev;
415 struct resource *pres, res;
416 int id, ret;
417
418 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
419 if (!pres) {
420 dev_err(&pdev->dev, "Invalid resource\n");
421 return -EINVAL;
422 }
423 memset(&res, 0, sizeof(res));
424 memset(&ppd, 0, sizeof(ppd));
425
426 ppd.wait_func = bcmgenet_mii_wait;
427 ppd.wait_func_data = priv;
428 ppd.bus_name = "bcmgenet MII bus";
429
430 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
431 * and is 2 * 32-bits word long, 8 bytes total.
432 */
433 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
434 res.end = res.start + 8;
435 res.flags = IORESOURCE_MEM;
436
437 if (dn)
438 id = of_alias_get_id(dn, "eth");
439 else
440 id = pdev->id;
441
442 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
443 if (!ppdev)
444 return -ENOMEM;
445
446 /* Retain this platform_device pointer for later cleanup */
447 priv->mii_pdev = ppdev;
448 ppdev->dev.parent = &pdev->dev;
449 if (dn)
450 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
451 else if (pdata)
452 bcmgenet_mii_pdata_init(priv, &ppd);
453 else
454 ppd.phy_mask = ~0;
455
456 ret = platform_device_add_resources(ppdev, &res, 1);
457 if (ret)
458 goto out;
459
460 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
461 if (ret)
462 goto out;
463
464 ret = platform_device_add(ppdev);
465 if (ret)
466 goto out;
467
468 return 0;
469 out:
470 platform_device_put(ppdev);
471 return ret;
472 }
473
bcmgenet_phy_interface_init(struct bcmgenet_priv * priv)474 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv)
475 {
476 struct device *kdev = &priv->pdev->dev;
477 int phy_mode = device_get_phy_mode(kdev);
478
479 if (phy_mode < 0) {
480 dev_err(kdev, "invalid PHY mode property\n");
481 return phy_mode;
482 }
483
484 priv->phy_interface = phy_mode;
485
486 /* We need to specifically look up whether this PHY interface is
487 * internal or not *before* we even try to probe the PHY driver
488 * over MDIO as we may have shut down the internal PHY for power
489 * saving purposes.
490 */
491 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
492 priv->internal_phy = true;
493
494 return 0;
495 }
496
bcmgenet_mii_of_init(struct bcmgenet_priv * priv)497 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
498 {
499 struct device_node *dn = priv->pdev->dev.of_node;
500 struct phy_device *phydev;
501 int ret;
502
503 /* Fetch the PHY phandle */
504 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
505
506 /* In the case of a fixed PHY, the DT node associated
507 * to the PHY is the Ethernet MAC DT node.
508 */
509 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
510 ret = of_phy_register_fixed_link(dn);
511 if (ret)
512 return ret;
513
514 priv->phy_dn = of_node_get(dn);
515 }
516
517 /* Get the link mode */
518 ret = bcmgenet_phy_interface_init(priv);
519 if (ret)
520 return ret;
521
522 /* Make sure we initialize MoCA PHYs with a link down */
523 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
524 phydev = of_phy_find_device(dn);
525 if (phydev) {
526 phydev->link = 0;
527 put_device(&phydev->mdio.dev);
528 }
529 }
530
531 return 0;
532 }
533
bcmgenet_mii_pd_init(struct bcmgenet_priv * priv)534 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
535 {
536 struct device *kdev = &priv->pdev->dev;
537 struct bcmgenet_platform_data *pd = kdev->platform_data;
538 char phy_name[MII_BUS_ID_SIZE + 3];
539 char mdio_bus_id[MII_BUS_ID_SIZE];
540 struct phy_device *phydev;
541
542 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
543 UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
544
545 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
546 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
547 mdio_bus_id, pd->phy_address);
548
549 /*
550 * Internal or external PHY with MDIO access
551 */
552 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
553 if (!phydev) {
554 dev_err(kdev, "failed to register PHY device\n");
555 return -ENODEV;
556 }
557 } else {
558 /*
559 * MoCA port or no MDIO access.
560 * Use fixed PHY to represent the link layer.
561 */
562 struct fixed_phy_status fphy_status = {
563 .link = 1,
564 .speed = pd->phy_speed,
565 .duplex = pd->phy_duplex,
566 .pause = 0,
567 .asym_pause = 0,
568 };
569
570 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
571 if (IS_ERR(phydev)) {
572 dev_err(kdev, "failed to register fixed PHY device\n");
573 return -ENODEV;
574 }
575
576 /* Make sure we initialize MoCA PHYs with a link down */
577 phydev->link = 0;
578
579 }
580
581 priv->phy_interface = pd->phy_interface;
582
583 return 0;
584 }
585
bcmgenet_mii_bus_init(struct bcmgenet_priv * priv)586 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
587 {
588 struct device *kdev = &priv->pdev->dev;
589 struct device_node *dn = kdev->of_node;
590
591 if (dn)
592 return bcmgenet_mii_of_init(priv);
593 else if (has_acpi_companion(kdev))
594 return bcmgenet_phy_interface_init(priv);
595 else
596 return bcmgenet_mii_pd_init(priv);
597 }
598
bcmgenet_mii_init(struct net_device * dev)599 int bcmgenet_mii_init(struct net_device *dev)
600 {
601 struct bcmgenet_priv *priv = netdev_priv(dev);
602 int ret;
603
604 ret = bcmgenet_mii_register(priv);
605 if (ret)
606 return ret;
607
608 ret = bcmgenet_mii_bus_init(priv);
609 if (ret)
610 goto out;
611
612 return 0;
613
614 out:
615 bcmgenet_mii_exit(dev);
616 return ret;
617 }
618
bcmgenet_mii_exit(struct net_device * dev)619 void bcmgenet_mii_exit(struct net_device *dev)
620 {
621 struct bcmgenet_priv *priv = netdev_priv(dev);
622 struct device_node *dn = priv->pdev->dev.of_node;
623
624 if (of_phy_is_fixed_link(dn))
625 of_phy_deregister_fixed_link(dn);
626 of_node_put(priv->phy_dn);
627 clk_prepare_enable(priv->clk);
628 platform_device_unregister(priv->mii_pdev);
629 clk_disable_unprepare(priv->clk);
630 }
631