1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40
41 /**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
53 *
54 */
55 struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61 };
62
63 /**
64 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
65 *
66 * @num: Numerator of the duty cycle ratio
67 * @den: Denominator of the duty cycle ratio
68 */
69 struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72 };
73
74 /**
75 * struct clk_ops - Callback operations for hardware clocks; these are to
76 * be provided by the clock implementation, and will be called by drivers
77 * through the clk_* api.
78 *
79 * @prepare: Prepare the clock for enabling. This must not return until
80 * the clock is fully prepared, and it's safe to call clk_enable.
81 * This callback is intended to allow clock implementations to
82 * do any initialisation that may sleep. Called with
83 * prepare_lock held.
84 *
85 * @unprepare: Release the clock from its prepared state. This will typically
86 * undo any work done in the @prepare callback. Called with
87 * prepare_lock held.
88 *
89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 * This function is allowed to sleep. Optional, if this op is not
91 * set then the prepare count will be used.
92 *
93 * @unprepare_unused: Unprepare the clock atomically. Only called from
94 * clk_disable_unused for prepare clocks with special needs.
95 * Called with prepare mutex held. This function may sleep.
96 *
97 * @enable: Enable the clock atomically. This must not return until the
98 * clock is generating a valid clock signal, usable by consumer
99 * devices. Called with enable_lock held. This function must not
100 * sleep.
101 *
102 * @disable: Disable the clock atomically. Called with enable_lock held.
103 * This function must not sleep.
104 *
105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 * This function must not sleep. Optional, if this op is not
107 * set then the enable count will be used.
108 *
109 * @disable_unused: Disable the clock atomically. Only called from
110 * clk_disable_unused for gate clocks with special needs.
111 * Called with enable_lock held. This function must not
112 * sleep.
113 *
114 * @save_context: Save the context of the clock in prepration for poweroff.
115 *
116 * @restore_context: Restore the context of the clock after a restoration
117 * of power.
118 *
119 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
121 * ensure that the prepare_mutex is held across this call.
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
124 *
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
127 * parameter.
128 *
129 * @determine_rate: Given a target rate as input, returns the closest rate
130 * actually supported by the clock, and optionally the parent clock
131 * that should be used to provide the clock rate.
132 *
133 * @set_parent: Change the input source of this clock; for clocks with multiple
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
136 * or .parents arrays. This function in affect translates an
137 * array index into the value programmed into the hardware.
138 * Returns 0 on success, -EERROR otherwise.
139 *
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
141 * return value is a u8 which specifies the index corresponding to
142 * the parent clock. This index can be applied to either the
143 * .parent_names or .parents arrays. In short, this function
144 * translates the parent value read from hardware into an array
145 * index. Currently only called when the clock is initialized by
146 * __clk_init. This callback is mandatory for clocks with
147 * multiple parents. It is optional (and unnecessary) for clocks
148 * with 0 or 1 parents.
149 *
150 * @set_rate: Change the rate of this clock. The requested rate is specified
151 * by the second argument, which should typically be the return
152 * of .round_rate call. The third argument gives the parent rate
153 * which is likely helpful for most .set_rate implementation.
154 * Returns 0 on success, -EERROR otherwise.
155 *
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
158 * should typically be the return of .round_rate call. The
159 * third argument gives the parent rate which is likely helpful
160 * for most .set_rate_and_parent implementation. The fourth
161 * argument gives the parent index. This callback is optional (and
162 * unnecessary) for clocks with 0 or 1 parents as well as
163 * for clocks that can tolerate switching the rate and the parent
164 * separately via calls to .set_parent and .set_rate.
165 * Returns 0 on success, -EERROR otherwise.
166 *
167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 * is expressed in ppb (parts per billion). The parent accuracy is
169 * an input parameter.
170 * Returns the calculated accuracy. Optional - if this op is not
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
173 *
174 * @get_phase: Queries the hardware to get the current phase of a clock.
175 * Returned values are 0-359 degrees on success, negative
176 * error codes on failure.
177 *
178 * @set_phase: Shift the phase this clock signal in degrees specified
179 * by the second argument. Valid values for degrees are
180 * 0-359. Return 0 on success, otherwise -EERROR.
181 *
182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 * of a clock. Returned values denominator cannot be 0 and must be
184 * superior or equal to the numerator.
185 *
186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 * the numerator (2nd argurment) and denominator (3rd argument).
188 * Argument must be a valid ratio (denominator > 0
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
190 *
191 * @init: Perform platform-specific initialization magic.
192 * This is not used by any of the basic clock types.
193 * This callback exist for HW which needs to perform some
194 * initialisation magic for CCF to get an accurate view of the
195 * clock. It may also be used dynamic resource allocation is
196 * required. It shall not used to deal with clock parameters,
197 * such as rate or parents.
198 * Returns 0 on success, -EERROR otherwise.
199 *
200 * @terminate: Free any resource allocated by init.
201 *
202 * @debug_init: Set up type-specific debugfs entries for this clock. This
203 * is called once, after the debugfs directory entry for this
204 * clock has been created. The dentry pointer representing that
205 * directory is provided as an argument. Called with
206 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
207 *
208 *
209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
210 * implementations to split any work between atomic (enable) and sleepable
211 * (prepare) contexts. If enabling a clock requires code that might sleep,
212 * this must be done in clk_prepare. Clock enable code that will never be
213 * called in a sleepable context may be implemented in clk_enable.
214 *
215 * Typically, drivers will call clk_prepare when a clock may be needed later
216 * (eg. when a device is opened), and clk_enable when the clock is actually
217 * required (eg. from an interrupt). Note that clk_prepare MUST have been
218 * called before clk_enable.
219 */
220 struct clk_ops {
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw,
232 unsigned long parent_rate);
233 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long *parent_rate);
235 int (*determine_rate)(struct clk_hw *hw,
236 struct clk_rate_request *req);
237 int (*set_parent)(struct clk_hw *hw, u8 index);
238 u8 (*get_parent)(struct clk_hw *hw);
239 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate);
241 int (*set_rate_and_parent)(struct clk_hw *hw,
242 unsigned long rate,
243 unsigned long parent_rate, u8 index);
244 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
245 unsigned long parent_accuracy);
246 int (*get_phase)(struct clk_hw *hw);
247 int (*set_phase)(struct clk_hw *hw, int degrees);
248 int (*get_duty_cycle)(struct clk_hw *hw,
249 struct clk_duty *duty);
250 int (*set_duty_cycle)(struct clk_hw *hw,
251 struct clk_duty *duty);
252 int (*init)(struct clk_hw *hw);
253 void (*terminate)(struct clk_hw *hw);
254 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
255 };
256
257 /**
258 * struct clk_parent_data - clk parent information
259 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
260 * @fw_name: parent name local to provider registering clk
261 * @name: globally unique parent name (used as a fallback)
262 * @index: parent index local to provider registering clk (if @fw_name absent)
263 */
264 struct clk_parent_data {
265 const struct clk_hw *hw;
266 const char *fw_name;
267 const char *name;
268 int index;
269 };
270
271 /**
272 * struct clk_init_data - holds init data that's common to all clocks and is
273 * shared between the clock provider and the common clock framework.
274 *
275 * @name: clock name
276 * @ops: operations this clock supports
277 * @parent_names: array of string names for all possible parents
278 * @parent_data: array of parent data for all possible parents (when some
279 * parents are external to the clk controller)
280 * @parent_hws: array of pointers to all possible parents (when all parents
281 * are internal to the clk controller)
282 * @num_parents: number of possible parents
283 * @flags: framework-level hints and quirks
284 */
285 struct clk_init_data {
286 const char *name;
287 const struct clk_ops *ops;
288 /* Only one of the following three should be assigned */
289 const char * const *parent_names;
290 const struct clk_parent_data *parent_data;
291 const struct clk_hw **parent_hws;
292 u8 num_parents;
293 unsigned long flags;
294 };
295
296 /**
297 * struct clk_hw - handle for traversing from a struct clk to its corresponding
298 * hardware-specific structure. struct clk_hw should be declared within struct
299 * clk_foo and then referenced by the struct clk instance that uses struct
300 * clk_foo's clk_ops
301 *
302 * @core: pointer to the struct clk_core instance that points back to this
303 * struct clk_hw instance
304 *
305 * @clk: pointer to the per-user struct clk instance that can be used to call
306 * into the clk API
307 *
308 * @init: pointer to struct clk_init_data that contains the init data shared
309 * with the common clock framework. This pointer will be set to NULL once
310 * a clk_register() variant is called on this clk_hw pointer.
311 */
312 struct clk_hw {
313 struct clk_core *core;
314 struct clk *clk;
315 const struct clk_init_data *init;
316 };
317
318 /*
319 * DOC: Basic clock implementations common to many platforms
320 *
321 * Each basic clock hardware type is comprised of a structure describing the
322 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
323 * unique flags for that hardware type, a registration function and an
324 * alternative macro for static initialization
325 */
326
327 /**
328 * struct clk_fixed_rate - fixed-rate clock
329 * @hw: handle between common and hardware-specific interfaces
330 * @fixed_rate: constant frequency of clock
331 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
332 * @flags: hardware specific flags
333 *
334 * Flags:
335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
336 * instead of what's set in @fixed_accuracy.
337 */
338 struct clk_fixed_rate {
339 struct clk_hw hw;
340 unsigned long fixed_rate;
341 unsigned long fixed_accuracy;
342 unsigned long flags;
343 };
344
345 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
346
347 extern const struct clk_ops clk_fixed_rate_ops;
348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
349 struct device_node *np, const char *name,
350 const char *parent_name, const struct clk_hw *parent_hw,
351 const struct clk_parent_data *parent_data, unsigned long flags,
352 unsigned long fixed_rate, unsigned long fixed_accuracy,
353 unsigned long clk_fixed_flags);
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
355 const char *parent_name, unsigned long flags,
356 unsigned long fixed_rate);
357 /**
358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
359 * framework
360 * @dev: device that is registering this clock
361 * @name: name of this clock
362 * @parent_name: name of clock's parent
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
365 */
366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
368 NULL, (flags), (fixed_rate), 0, 0)
369 /**
370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
371 * the clock framework
372 * @dev: device that is registering this clock
373 * @name: name of this clock
374 * @parent_hw: pointer to parent clk
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
377 */
378 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
379 fixed_rate) \
380 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
381 NULL, (flags), (fixed_rate), 0, 0)
382 /**
383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
384 * the clock framework
385 * @dev: device that is registering this clock
386 * @name: name of this clock
387 * @parent_data: parent clk data
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
390 */
391 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
392 fixed_rate) \
393 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
394 (parent_data), (flags), (fixed_rate), 0, \
395 0)
396 /**
397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_name: name of clock's parent
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 * @fixed_accuracy: non-adjustable clock accuracy
405 */
406 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
407 flags, fixed_rate, \
408 fixed_accuracy) \
409 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
410 NULL, NULL, (flags), (fixed_rate), \
411 (fixed_accuracy), 0)
412 /**
413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
414 * clock with the clock framework
415 * @dev: device that is registering this clock
416 * @name: name of this clock
417 * @parent_hw: pointer to parent clk
418 * @flags: framework-specific flags
419 * @fixed_rate: non-adjustable clock rate
420 * @fixed_accuracy: non-adjustable clock accuracy
421 */
422 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
423 parent_hw, flags, fixed_rate, fixed_accuracy) \
424 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
425 NULL, NULL, (flags), (fixed_rate), \
426 (fixed_accuracy), 0)
427 /**
428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
429 * clock with the clock framework
430 * @dev: device that is registering this clock
431 * @name: name of this clock
432 * @parent_data: name of clock's parent
433 * @flags: framework-specific flags
434 * @fixed_rate: non-adjustable clock rate
435 * @fixed_accuracy: non-adjustable clock accuracy
436 */
437 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
438 parent_data, flags, fixed_rate, fixed_accuracy) \
439 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
440 (parent_data), NULL, (flags), \
441 (fixed_rate), (fixed_accuracy), 0)
442 /**
443 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
444 * the clock framework
445 * @dev: device that is registering this clock
446 * @name: name of this clock
447 * @parent_data: name of clock's parent
448 * @flags: framework-specific flags
449 * @fixed_rate: non-adjustable clock rate
450 */
451 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
452 flags, fixed_rate) \
453 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
454 (parent_data), (flags), (fixed_rate), 0, \
455 CLK_FIXED_RATE_PARENT_ACCURACY)
456
457 void clk_unregister_fixed_rate(struct clk *clk);
458 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
459
460 void of_fixed_clk_setup(struct device_node *np);
461
462 /**
463 * struct clk_gate - gating clock
464 *
465 * @hw: handle between common and hardware-specific interfaces
466 * @reg: register controlling gate
467 * @bit_idx: single bit controlling gate
468 * @flags: hardware-specific flags
469 * @lock: register lock
470 *
471 * Clock which can gate its output. Implements .enable & .disable
472 *
473 * Flags:
474 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
475 * enable the clock. Setting this flag does the opposite: setting the bit
476 * disable the clock and clearing it enables the clock
477 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
478 * of this register, and mask of gate bits are in higher 16-bit of this
479 * register. While setting the gate bits, higher 16-bit should also be
480 * updated to indicate changing gate bits.
481 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
482 * the gate register. Setting this flag makes the register accesses big
483 * endian.
484 */
485 struct clk_gate {
486 struct clk_hw hw;
487 void __iomem *reg;
488 u8 bit_idx;
489 u8 flags;
490 spinlock_t *lock;
491 };
492
493 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
494
495 #define CLK_GATE_SET_TO_DISABLE BIT(0)
496 #define CLK_GATE_HIWORD_MASK BIT(1)
497 #define CLK_GATE_BIG_ENDIAN BIT(2)
498
499 extern const struct clk_ops clk_gate_ops;
500 struct clk_hw *__clk_hw_register_gate(struct device *dev,
501 struct device_node *np, const char *name,
502 const char *parent_name, const struct clk_hw *parent_hw,
503 const struct clk_parent_data *parent_data,
504 unsigned long flags,
505 void __iomem *reg, u8 bit_idx,
506 u8 clk_gate_flags, spinlock_t *lock);
507 struct clk *clk_register_gate(struct device *dev, const char *name,
508 const char *parent_name, unsigned long flags,
509 void __iomem *reg, u8 bit_idx,
510 u8 clk_gate_flags, spinlock_t *lock);
511 /**
512 * clk_hw_register_gate - register a gate clock with the clock framework
513 * @dev: device that is registering this clock
514 * @name: name of this clock
515 * @parent_name: name of this clock's parent
516 * @flags: framework-specific flags for this clock
517 * @reg: register address to control gating of this clock
518 * @bit_idx: which bit in the register controls gating of this clock
519 * @clk_gate_flags: gate-specific flags for this clock
520 * @lock: shared register lock for this clock
521 */
522 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
523 clk_gate_flags, lock) \
524 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
525 NULL, (flags), (reg), (bit_idx), \
526 (clk_gate_flags), (lock))
527 /**
528 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
529 * framework
530 * @dev: device that is registering this clock
531 * @name: name of this clock
532 * @parent_hw: pointer to parent clk
533 * @flags: framework-specific flags for this clock
534 * @reg: register address to control gating of this clock
535 * @bit_idx: which bit in the register controls gating of this clock
536 * @clk_gate_flags: gate-specific flags for this clock
537 * @lock: shared register lock for this clock
538 */
539 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
540 bit_idx, clk_gate_flags, lock) \
541 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
542 NULL, (flags), (reg), (bit_idx), \
543 (clk_gate_flags), (lock))
544 /**
545 * clk_hw_register_gate_parent_data - register a gate clock with the clock
546 * framework
547 * @dev: device that is registering this clock
548 * @name: name of this clock
549 * @parent_data: parent clk data
550 * @flags: framework-specific flags for this clock
551 * @reg: register address to control gating of this clock
552 * @bit_idx: which bit in the register controls gating of this clock
553 * @clk_gate_flags: gate-specific flags for this clock
554 * @lock: shared register lock for this clock
555 */
556 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
557 bit_idx, clk_gate_flags, lock) \
558 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
559 (flags), (reg), (bit_idx), \
560 (clk_gate_flags), (lock))
561 void clk_unregister_gate(struct clk *clk);
562 void clk_hw_unregister_gate(struct clk_hw *hw);
563 int clk_gate_is_enabled(struct clk_hw *hw);
564
565 struct clk_div_table {
566 unsigned int val;
567 unsigned int div;
568 };
569
570 /**
571 * struct clk_divider - adjustable divider clock
572 *
573 * @hw: handle between common and hardware-specific interfaces
574 * @reg: register containing the divider
575 * @shift: shift to the divider bit field
576 * @width: width of the divider bit field
577 * @table: array of value/divider pairs, last entry should have div = 0
578 * @lock: register lock
579 *
580 * Clock with an adjustable divider affecting its output frequency. Implements
581 * .recalc_rate, .set_rate and .round_rate
582 *
583 * @flags:
584 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
585 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
586 * the raw value read from the register, with the value of zero considered
587 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
588 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
589 * the hardware register
590 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
591 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
592 * Some hardware implementations gracefully handle this case and allow a
593 * zero divisor by not modifying their input clock
594 * (divide by one / bypass).
595 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
596 * of this register, and mask of divider bits are in higher 16-bit of this
597 * register. While setting the divider bits, higher 16-bit should also be
598 * updated to indicate changing divider bits.
599 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
600 * to the closest integer instead of the up one.
601 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
602 * not be changed by the clock framework.
603 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
604 * except when the value read from the register is zero, the divisor is
605 * 2^width of the field.
606 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
607 * for the divider register. Setting this flag makes the register accesses
608 * big endian.
609 */
610 struct clk_divider {
611 struct clk_hw hw;
612 void __iomem *reg;
613 u8 shift;
614 u8 width;
615 u8 flags;
616 const struct clk_div_table *table;
617 spinlock_t *lock;
618 };
619
620 #define clk_div_mask(width) ((1 << (width)) - 1)
621 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
622
623 #define CLK_DIVIDER_ONE_BASED BIT(0)
624 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
625 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
626 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
627 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
628 #define CLK_DIVIDER_READ_ONLY BIT(5)
629 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
630 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
631
632 extern const struct clk_ops clk_divider_ops;
633 extern const struct clk_ops clk_divider_ro_ops;
634
635 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
636 unsigned int val, const struct clk_div_table *table,
637 unsigned long flags, unsigned long width);
638 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
639 unsigned long rate, unsigned long *prate,
640 const struct clk_div_table *table,
641 u8 width, unsigned long flags);
642 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
643 unsigned long rate, unsigned long *prate,
644 const struct clk_div_table *table, u8 width,
645 unsigned long flags, unsigned int val);
646 int divider_get_val(unsigned long rate, unsigned long parent_rate,
647 const struct clk_div_table *table, u8 width,
648 unsigned long flags);
649
650 struct clk_hw *__clk_hw_register_divider(struct device *dev,
651 struct device_node *np, const char *name,
652 const char *parent_name, const struct clk_hw *parent_hw,
653 const struct clk_parent_data *parent_data, unsigned long flags,
654 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
655 const struct clk_div_table *table, spinlock_t *lock);
656 struct clk *clk_register_divider_table(struct device *dev, const char *name,
657 const char *parent_name, unsigned long flags,
658 void __iomem *reg, u8 shift, u8 width,
659 u8 clk_divider_flags, const struct clk_div_table *table,
660 spinlock_t *lock);
661 /**
662 * clk_register_divider - register a divider clock with the clock framework
663 * @dev: device registering this clock
664 * @name: name of this clock
665 * @parent_name: name of clock's parent
666 * @flags: framework-specific flags
667 * @reg: register address to adjust divider
668 * @shift: number of bits to shift the bitfield
669 * @width: width of the bitfield
670 * @clk_divider_flags: divider-specific flags for this clock
671 * @lock: shared register lock for this clock
672 */
673 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
674 clk_divider_flags, lock) \
675 clk_register_divider_table((dev), (name), (parent_name), (flags), \
676 (reg), (shift), (width), \
677 (clk_divider_flags), NULL, (lock))
678 /**
679 * clk_hw_register_divider - register a divider clock with the clock framework
680 * @dev: device registering this clock
681 * @name: name of this clock
682 * @parent_name: name of clock's parent
683 * @flags: framework-specific flags
684 * @reg: register address to adjust divider
685 * @shift: number of bits to shift the bitfield
686 * @width: width of the bitfield
687 * @clk_divider_flags: divider-specific flags for this clock
688 * @lock: shared register lock for this clock
689 */
690 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
691 width, clk_divider_flags, lock) \
692 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
693 NULL, (flags), (reg), (shift), (width), \
694 (clk_divider_flags), NULL, (lock))
695 /**
696 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
697 * framework
698 * @dev: device registering this clock
699 * @name: name of this clock
700 * @parent_hw: pointer to parent clk
701 * @flags: framework-specific flags
702 * @reg: register address to adjust divider
703 * @shift: number of bits to shift the bitfield
704 * @width: width of the bitfield
705 * @clk_divider_flags: divider-specific flags for this clock
706 * @lock: shared register lock for this clock
707 */
708 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
709 shift, width, clk_divider_flags, \
710 lock) \
711 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
712 NULL, (flags), (reg), (shift), (width), \
713 (clk_divider_flags), NULL, (lock))
714 /**
715 * clk_hw_register_divider_parent_data - register a divider clock with the clock
716 * framework
717 * @dev: device registering this clock
718 * @name: name of this clock
719 * @parent_data: parent clk data
720 * @flags: framework-specific flags
721 * @reg: register address to adjust divider
722 * @shift: number of bits to shift the bitfield
723 * @width: width of the bitfield
724 * @clk_divider_flags: divider-specific flags for this clock
725 * @lock: shared register lock for this clock
726 */
727 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
728 reg, shift, width, \
729 clk_divider_flags, lock) \
730 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
731 (parent_data), (flags), (reg), (shift), \
732 (width), (clk_divider_flags), NULL, (lock))
733 /**
734 * clk_hw_register_divider_table - register a table based divider clock with
735 * the clock framework
736 * @dev: device registering this clock
737 * @name: name of this clock
738 * @parent_name: name of clock's parent
739 * @flags: framework-specific flags
740 * @reg: register address to adjust divider
741 * @shift: number of bits to shift the bitfield
742 * @width: width of the bitfield
743 * @clk_divider_flags: divider-specific flags for this clock
744 * @table: array of divider/value pairs ending with a div set to 0
745 * @lock: shared register lock for this clock
746 */
747 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
748 shift, width, clk_divider_flags, table, \
749 lock) \
750 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
751 NULL, (flags), (reg), (shift), (width), \
752 (clk_divider_flags), (table), (lock))
753 /**
754 * clk_hw_register_divider_table_parent_hw - register a table based divider
755 * clock with the clock framework
756 * @dev: device registering this clock
757 * @name: name of this clock
758 * @parent_hw: pointer to parent clk
759 * @flags: framework-specific flags
760 * @reg: register address to adjust divider
761 * @shift: number of bits to shift the bitfield
762 * @width: width of the bitfield
763 * @clk_divider_flags: divider-specific flags for this clock
764 * @table: array of divider/value pairs ending with a div set to 0
765 * @lock: shared register lock for this clock
766 */
767 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
768 reg, shift, width, \
769 clk_divider_flags, table, \
770 lock) \
771 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
772 NULL, (flags), (reg), (shift), (width), \
773 (clk_divider_flags), (table), (lock))
774 /**
775 * clk_hw_register_divider_table_parent_data - register a table based divider
776 * clock with the clock framework
777 * @dev: device registering this clock
778 * @name: name of this clock
779 * @parent_data: parent clk data
780 * @flags: framework-specific flags
781 * @reg: register address to adjust divider
782 * @shift: number of bits to shift the bitfield
783 * @width: width of the bitfield
784 * @clk_divider_flags: divider-specific flags for this clock
785 * @table: array of divider/value pairs ending with a div set to 0
786 * @lock: shared register lock for this clock
787 */
788 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
789 flags, reg, shift, width, \
790 clk_divider_flags, table, \
791 lock) \
792 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
793 (parent_data), (flags), (reg), (shift), \
794 (width), (clk_divider_flags), (table), \
795 (lock))
796
797 void clk_unregister_divider(struct clk *clk);
798 void clk_hw_unregister_divider(struct clk_hw *hw);
799
800 /**
801 * struct clk_mux - multiplexer clock
802 *
803 * @hw: handle between common and hardware-specific interfaces
804 * @reg: register controlling multiplexer
805 * @table: array of register values corresponding to the parent index
806 * @shift: shift to multiplexer bit field
807 * @mask: mask of mutliplexer bit field
808 * @flags: hardware-specific flags
809 * @lock: register lock
810 *
811 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
812 * and .recalc_rate
813 *
814 * Flags:
815 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
816 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
817 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
818 * register, and mask of mux bits are in higher 16-bit of this register.
819 * While setting the mux bits, higher 16-bit should also be updated to
820 * indicate changing mux bits.
821 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
822 * .get_parent clk_op.
823 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
824 * frequency.
825 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
826 * the mux register. Setting this flag makes the register accesses big
827 * endian.
828 */
829 struct clk_mux {
830 struct clk_hw hw;
831 void __iomem *reg;
832 u32 *table;
833 u32 mask;
834 u8 shift;
835 u8 flags;
836 spinlock_t *lock;
837 };
838
839 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
840
841 #define CLK_MUX_INDEX_ONE BIT(0)
842 #define CLK_MUX_INDEX_BIT BIT(1)
843 #define CLK_MUX_HIWORD_MASK BIT(2)
844 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
845 #define CLK_MUX_ROUND_CLOSEST BIT(4)
846 #define CLK_MUX_BIG_ENDIAN BIT(5)
847
848 extern const struct clk_ops clk_mux_ops;
849 extern const struct clk_ops clk_mux_ro_ops;
850
851 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
852 const char *name, u8 num_parents,
853 const char * const *parent_names,
854 const struct clk_hw **parent_hws,
855 const struct clk_parent_data *parent_data,
856 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
857 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
858 struct clk *clk_register_mux_table(struct device *dev, const char *name,
859 const char * const *parent_names, u8 num_parents,
860 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
861 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
862
863 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
864 shift, width, clk_mux_flags, lock) \
865 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
866 (flags), (reg), (shift), BIT((width)) - 1, \
867 (clk_mux_flags), NULL, (lock))
868 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
869 flags, reg, shift, mask, clk_mux_flags, \
870 table, lock) \
871 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
872 (parent_names), NULL, NULL, (flags), (reg), \
873 (shift), (mask), (clk_mux_flags), (table), \
874 (lock))
875 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
876 num_parents, flags, reg, shift, mask, \
877 clk_mux_flags, table, lock) \
878 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
879 NULL, NULL, (parent_data), (flags), (reg), \
880 (shift), (mask), (clk_mux_flags), (table), \
881 (lock))
882 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
883 shift, width, clk_mux_flags, lock) \
884 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
885 (parent_names), NULL, NULL, (flags), (reg), \
886 (shift), BIT((width)) - 1, (clk_mux_flags), \
887 NULL, (lock))
888 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
889 reg, shift, width, clk_mux_flags, lock) \
890 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
891 (parent_hws), NULL, (flags), (reg), (shift), \
892 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
893 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
894 flags, reg, shift, width, \
895 clk_mux_flags, lock) \
896 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
897 (parent_data), (flags), (reg), (shift), \
898 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
899
900 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
901 unsigned int val);
902 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
903
904 void clk_unregister_mux(struct clk *clk);
905 void clk_hw_unregister_mux(struct clk_hw *hw);
906
907 void of_fixed_factor_clk_setup(struct device_node *node);
908
909 /**
910 * struct clk_fixed_factor - fixed multiplier and divider clock
911 *
912 * @hw: handle between common and hardware-specific interfaces
913 * @mult: multiplier
914 * @div: divider
915 *
916 * Clock with a fixed multiplier and divider. The output frequency is the
917 * parent clock rate divided by div and multiplied by mult.
918 * Implements .recalc_rate, .set_rate and .round_rate
919 */
920
921 struct clk_fixed_factor {
922 struct clk_hw hw;
923 unsigned int mult;
924 unsigned int div;
925 };
926
927 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
928
929 extern const struct clk_ops clk_fixed_factor_ops;
930 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
931 const char *parent_name, unsigned long flags,
932 unsigned int mult, unsigned int div);
933 void clk_unregister_fixed_factor(struct clk *clk);
934 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
935 const char *name, const char *parent_name, unsigned long flags,
936 unsigned int mult, unsigned int div);
937 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
938
939 /**
940 * struct clk_fractional_divider - adjustable fractional divider clock
941 *
942 * @hw: handle between common and hardware-specific interfaces
943 * @reg: register containing the divider
944 * @mshift: shift to the numerator bit field
945 * @mwidth: width of the numerator bit field
946 * @nshift: shift to the denominator bit field
947 * @nwidth: width of the denominator bit field
948 * @approximation: clk driver's callback for calculating the divider clock
949 * @lock: register lock
950 *
951 * Clock with adjustable fractional divider affecting its output frequency.
952 *
953 * @flags:
954 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
955 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
956 * is set then the numerator and denominator are both the value read
957 * plus one.
958 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
959 * used for the divider register. Setting this flag makes the register
960 * accesses big endian.
961 */
962 struct clk_fractional_divider {
963 struct clk_hw hw;
964 void __iomem *reg;
965 u8 mshift;
966 u8 mwidth;
967 u32 mmask;
968 u8 nshift;
969 u8 nwidth;
970 u32 nmask;
971 u8 flags;
972 void (*approximation)(struct clk_hw *hw,
973 unsigned long rate, unsigned long *parent_rate,
974 unsigned long *m, unsigned long *n);
975 spinlock_t *lock;
976 };
977
978 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
979
980 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
981 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
982
983 extern const struct clk_ops clk_fractional_divider_ops;
984 struct clk *clk_register_fractional_divider(struct device *dev,
985 const char *name, const char *parent_name, unsigned long flags,
986 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
987 u8 clk_divider_flags, spinlock_t *lock);
988 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
989 const char *name, const char *parent_name, unsigned long flags,
990 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
991 u8 clk_divider_flags, spinlock_t *lock);
992 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
993
994 /**
995 * struct clk_multiplier - adjustable multiplier clock
996 *
997 * @hw: handle between common and hardware-specific interfaces
998 * @reg: register containing the multiplier
999 * @shift: shift to the multiplier bit field
1000 * @width: width of the multiplier bit field
1001 * @lock: register lock
1002 *
1003 * Clock with an adjustable multiplier affecting its output frequency.
1004 * Implements .recalc_rate, .set_rate and .round_rate
1005 *
1006 * @flags:
1007 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1008 * from the register, with 0 being a valid value effectively
1009 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1010 * set, then a null multiplier will be considered as a bypass,
1011 * leaving the parent rate unmodified.
1012 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1013 * rounded to the closest integer instead of the down one.
1014 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1015 * used for the multiplier register. Setting this flag makes the register
1016 * accesses big endian.
1017 */
1018 struct clk_multiplier {
1019 struct clk_hw hw;
1020 void __iomem *reg;
1021 u8 shift;
1022 u8 width;
1023 u8 flags;
1024 spinlock_t *lock;
1025 };
1026
1027 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1028
1029 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1030 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1031 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1032
1033 extern const struct clk_ops clk_multiplier_ops;
1034
1035 /***
1036 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1037 *
1038 * @hw: handle between common and hardware-specific interfaces
1039 * @mux_hw: handle between composite and hardware-specific mux clock
1040 * @rate_hw: handle between composite and hardware-specific rate clock
1041 * @gate_hw: handle between composite and hardware-specific gate clock
1042 * @mux_ops: clock ops for mux
1043 * @rate_ops: clock ops for rate
1044 * @gate_ops: clock ops for gate
1045 */
1046 struct clk_composite {
1047 struct clk_hw hw;
1048 struct clk_ops ops;
1049
1050 struct clk_hw *mux_hw;
1051 struct clk_hw *rate_hw;
1052 struct clk_hw *gate_hw;
1053
1054 const struct clk_ops *mux_ops;
1055 const struct clk_ops *rate_ops;
1056 const struct clk_ops *gate_ops;
1057 };
1058
1059 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1060
1061 struct clk *clk_register_composite(struct device *dev, const char *name,
1062 const char * const *parent_names, int num_parents,
1063 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1064 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1065 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1066 unsigned long flags);
1067 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1068 const struct clk_parent_data *parent_data, int num_parents,
1069 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1070 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1071 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1072 unsigned long flags);
1073 void clk_unregister_composite(struct clk *clk);
1074 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1075 const char * const *parent_names, int num_parents,
1076 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1077 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1078 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1079 unsigned long flags);
1080 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1081 const char *name,
1082 const struct clk_parent_data *parent_data, int num_parents,
1083 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1084 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1085 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1086 unsigned long flags);
1087 void clk_hw_unregister_composite(struct clk_hw *hw);
1088
1089 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1090 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1091
1092 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1093 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1094 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1095
1096 void clk_unregister(struct clk *clk);
1097 void devm_clk_unregister(struct device *dev, struct clk *clk);
1098
1099 void clk_hw_unregister(struct clk_hw *hw);
1100 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1101
1102 /* helper functions */
1103 const char *__clk_get_name(const struct clk *clk);
1104 const char *clk_hw_get_name(const struct clk_hw *hw);
1105 #ifdef CONFIG_COMMON_CLK
1106 struct clk_hw *__clk_get_hw(struct clk *clk);
1107 #else
__clk_get_hw(struct clk * clk)1108 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1109 {
1110 return (struct clk_hw *)clk;
1111 }
1112 #endif
1113 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1114 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1115 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1116 unsigned int index);
1117 int clk_hw_get_parent_index(struct clk_hw *hw);
1118 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1119 unsigned int __clk_get_enable_count(struct clk *clk);
1120 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1121 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1122 #define clk_hw_can_set_rate_parent(hw) \
1123 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1124
1125 bool clk_hw_is_prepared(const struct clk_hw *hw);
1126 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1127 bool clk_hw_is_enabled(const struct clk_hw *hw);
1128 bool __clk_is_enabled(struct clk *clk);
1129 struct clk *__clk_lookup(const char *name);
1130 int __clk_mux_determine_rate(struct clk_hw *hw,
1131 struct clk_rate_request *req);
1132 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1133 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1134 struct clk_rate_request *req);
1135 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1136 struct clk_rate_request *req,
1137 unsigned long flags);
1138 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1139 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1140 unsigned long max_rate);
1141
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1142 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1143 {
1144 dst->clk = src->clk;
1145 dst->core = src->core;
1146 }
1147
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1148 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1149 unsigned long *prate,
1150 const struct clk_div_table *table,
1151 u8 width, unsigned long flags)
1152 {
1153 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1154 rate, prate, table, width, flags);
1155 }
1156
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1157 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1158 unsigned long *prate,
1159 const struct clk_div_table *table,
1160 u8 width, unsigned long flags,
1161 unsigned int val)
1162 {
1163 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1164 rate, prate, table, width, flags,
1165 val);
1166 }
1167
1168 /*
1169 * FIXME clock api without lock protection
1170 */
1171 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1172
1173 struct clk_onecell_data {
1174 struct clk **clks;
1175 unsigned int clk_num;
1176 };
1177
1178 struct clk_hw_onecell_data {
1179 unsigned int num;
1180 struct clk_hw *hws[];
1181 };
1182
1183 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1184
1185 /*
1186 * Use this macro when you have a driver that requires two initialization
1187 * routines, one at of_clk_init(), and one at platform device probe
1188 */
1189 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1190 static void __init name##_of_clk_init_driver(struct device_node *np) \
1191 { \
1192 of_node_clear_flag(np, OF_POPULATED); \
1193 fn(np); \
1194 } \
1195 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1196
1197 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1198 (&(struct clk_init_data) { \
1199 .flags = _flags, \
1200 .name = _name, \
1201 .parent_names = (const char *[]) { _parent }, \
1202 .num_parents = 1, \
1203 .ops = _ops, \
1204 })
1205
1206 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1207 (&(struct clk_init_data) { \
1208 .flags = _flags, \
1209 .name = _name, \
1210 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1211 .num_parents = 1, \
1212 .ops = _ops, \
1213 })
1214
1215 /*
1216 * This macro is intended for drivers to be able to share the otherwise
1217 * individual struct clk_hw[] compound literals created by the compiler
1218 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1219 */
1220 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1221 (&(struct clk_init_data) { \
1222 .flags = _flags, \
1223 .name = _name, \
1224 .parent_hws = _parent, \
1225 .num_parents = 1, \
1226 .ops = _ops, \
1227 })
1228
1229 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1230 (&(struct clk_init_data) { \
1231 .flags = _flags, \
1232 .name = _name, \
1233 .parent_data = (const struct clk_parent_data[]) { \
1234 { .fw_name = _parent }, \
1235 }, \
1236 .num_parents = 1, \
1237 .ops = _ops, \
1238 })
1239
1240 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1241 (&(struct clk_init_data) { \
1242 .flags = _flags, \
1243 .name = _name, \
1244 .parent_names = _parents, \
1245 .num_parents = ARRAY_SIZE(_parents), \
1246 .ops = _ops, \
1247 })
1248
1249 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1250 (&(struct clk_init_data) { \
1251 .flags = _flags, \
1252 .name = _name, \
1253 .parent_hws = _parents, \
1254 .num_parents = ARRAY_SIZE(_parents), \
1255 .ops = _ops, \
1256 })
1257
1258 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1259 (&(struct clk_init_data) { \
1260 .flags = _flags, \
1261 .name = _name, \
1262 .parent_data = _parents, \
1263 .num_parents = ARRAY_SIZE(_parents), \
1264 .ops = _ops, \
1265 })
1266
1267 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1268 (&(struct clk_init_data) { \
1269 .flags = _flags, \
1270 .name = _name, \
1271 .parent_names = NULL, \
1272 .num_parents = 0, \
1273 .ops = _ops, \
1274 })
1275
1276 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1277 _div, _mult, _flags) \
1278 struct clk_fixed_factor _struct = { \
1279 .div = _div, \
1280 .mult = _mult, \
1281 .hw.init = CLK_HW_INIT(_name, \
1282 _parent, \
1283 &clk_fixed_factor_ops, \
1284 _flags), \
1285 }
1286
1287 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1288 _div, _mult, _flags) \
1289 struct clk_fixed_factor _struct = { \
1290 .div = _div, \
1291 .mult = _mult, \
1292 .hw.init = CLK_HW_INIT_HW(_name, \
1293 _parent, \
1294 &clk_fixed_factor_ops, \
1295 _flags), \
1296 }
1297
1298 /*
1299 * This macro allows the driver to reuse the _parent array for multiple
1300 * fixed factor clk declarations.
1301 */
1302 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1303 _div, _mult, _flags) \
1304 struct clk_fixed_factor _struct = { \
1305 .div = _div, \
1306 .mult = _mult, \
1307 .hw.init = CLK_HW_INIT_HWS(_name, \
1308 _parent, \
1309 &clk_fixed_factor_ops, \
1310 _flags), \
1311 }
1312
1313 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1314 _div, _mult, _flags) \
1315 struct clk_fixed_factor _struct = { \
1316 .div = _div, \
1317 .mult = _mult, \
1318 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1319 _parent, \
1320 &clk_fixed_factor_ops, \
1321 _flags), \
1322 }
1323
1324 #ifdef CONFIG_OF
1325 int of_clk_add_provider(struct device_node *np,
1326 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1327 void *data),
1328 void *data);
1329 int of_clk_add_hw_provider(struct device_node *np,
1330 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1331 void *data),
1332 void *data);
1333 int devm_of_clk_add_hw_provider(struct device *dev,
1334 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1335 void *data),
1336 void *data);
1337 void of_clk_del_provider(struct device_node *np);
1338 void devm_of_clk_del_provider(struct device *dev);
1339 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1340 void *data);
1341 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1342 void *data);
1343 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1344 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1345 void *data);
1346 int of_clk_parent_fill(struct device_node *np, const char **parents,
1347 unsigned int size);
1348 int of_clk_detect_critical(struct device_node *np, int index,
1349 unsigned long *flags);
1350
1351 #else /* !CONFIG_OF */
1352
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1353 static inline int of_clk_add_provider(struct device_node *np,
1354 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1355 void *data),
1356 void *data)
1357 {
1358 return 0;
1359 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1360 static inline int of_clk_add_hw_provider(struct device_node *np,
1361 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1362 void *data),
1363 void *data)
1364 {
1365 return 0;
1366 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1367 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1368 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1369 void *data),
1370 void *data)
1371 {
1372 return 0;
1373 }
of_clk_del_provider(struct device_node * np)1374 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1375 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1376 static inline struct clk *of_clk_src_simple_get(
1377 struct of_phandle_args *clkspec, void *data)
1378 {
1379 return ERR_PTR(-ENOENT);
1380 }
1381 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1382 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1383 {
1384 return ERR_PTR(-ENOENT);
1385 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1386 static inline struct clk *of_clk_src_onecell_get(
1387 struct of_phandle_args *clkspec, void *data)
1388 {
1389 return ERR_PTR(-ENOENT);
1390 }
1391 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1392 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1393 {
1394 return ERR_PTR(-ENOENT);
1395 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1396 static inline int of_clk_parent_fill(struct device_node *np,
1397 const char **parents, unsigned int size)
1398 {
1399 return 0;
1400 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1401 static inline int of_clk_detect_critical(struct device_node *np, int index,
1402 unsigned long *flags)
1403 {
1404 return 0;
1405 }
1406 #endif /* CONFIG_OF */
1407
1408 void clk_gate_restore_context(struct clk_hw *hw);
1409
1410 #endif /* CLK_PROVIDER_H */
1411