1commit b2ead3ad6b2c5b83367b9e09d567206238b6dcef 2Author: zhaoxc0502 <zhaoxc0502@thundersoft.com> 3Date: Thu Jun 16 17:20:47 2022 +0800 4 5 linux_drivers_i2c 6 7 Change-Id: I4a66d5b97f61e6f70ee3a088441bee616aff2012 8 9diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig 10index 7e693dcbd..f01861bbc 100644 11--- a/drivers/i2c/busses/Kconfig 12+++ b/drivers/i2c/busses/Kconfig 13@@ -692,6 +692,14 @@ config I2C_IMX_LPI2C 14 This driver can also be built as a module. If so, the module 15 will be called i2c-imx-lpi2c. 16 17+config I2C_IMX_FLEXIO 18+ tristate "NXP IMX FLEXIO I2C MASTER" 19+ depends on ARCH_MXC || COMPILE_TEST 20+ default y 21+ help 22+ If you say yes to this option, support will be included for the 23+ I2C controller simulated by flexio embedded in NXP IMX8ULP SOCs. 24+ 25 config I2C_IOP3XX 26 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" 27 depends on ARCH_IOP32X || ARCH_IXP4XX || COMPILE_TEST 28@@ -954,6 +962,12 @@ config I2C_RK3X 29 This driver can also be built as a module. If so, the module will 30 be called i2c-rk3x. 31 32+config I2C_RPBUS 33+ tristate "I2C proxy bus over RPMSG" 34+ depends on I2C && RPMSG 35+ help 36+ This driver can support virtual i2c-rpmsg function. 37+ 38 config HAVE_S3C2410_I2C 39 bool 40 help 41@@ -1420,4 +1434,14 @@ config I2C_FSI 42 This driver can also be built as a module. If so, the module will be 43 called as i2c-fsi. 44 45+config XEN_I2C_FRONTEND 46+ tristate "Xen virtual i2c device support" 47+ depends on XEN 48+ default y 49+ select XEN_XENBUS_FRONTEND 50+ help 51+ This driver implements the front-end of the Xen virtual 52+ i2c device driver. It communicates with a back-end driver 53+ in another domain which drives the actual i2c device. 54+ 55 endmenu 56diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile 57index 683c49fac..92ebaccce 100644 58--- a/drivers/i2c/busses/Makefile 59+++ b/drivers/i2c/busses/Makefile 60@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 61 obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o 62 obj-$(CONFIG_I2C_IMX) += i2c-imx.o 63 obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-lpi2c.o 64+obj-$(CONFIG_I2C_IMX_FLEXIO) += i2c-flexio.o 65 obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o 66 obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o 67 obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o 68@@ -129,6 +130,7 @@ obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o 69 obj-$(CONFIG_I2C_DLN2) += i2c-dln2.o 70 obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o 71 obj-$(CONFIG_I2C_ROBOTFUZZ_OSIF) += i2c-robotfuzz-osif.o 72+obj-$(CONFIG_I2C_RPBUS) += i2c-rpmsg-imx.o 73 obj-$(CONFIG_I2C_TAOS_EVM) += i2c-taos-evm.o 74 obj-$(CONFIG_I2C_TINY_USB) += i2c-tiny-usb.o 75 obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o 76@@ -149,4 +151,5 @@ obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o 77 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o 78 obj-$(CONFIG_I2C_FSI) += i2c-fsi.o 79 80+obj-$(CONFIG_XEN_I2C_FRONTEND) += xen-i2cfront.o 81 ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG 82diff --git a/drivers/i2c/busses/i2c-flexio.c b/drivers/i2c/busses/i2c-flexio.c 83new file mode 100644 84index 000000000..4d80417eb 85--- /dev/null 86+++ b/drivers/i2c/busses/i2c-flexio.c 87@@ -0,0 +1,994 @@ 88+// SPDX-License-Identifier: GPL-2.0-only 89+/* 90+ * flexio i2c master driver 91+ * 92+ * Copyright 2021 NXP 93+ * 94+ * Author: Alice Guo <alice.guo@nxp.com> 95+ */ 96+ 97+#include <linux/clk.h> 98+#include <linux/completion.h> 99+#include <linux/i2c.h> 100+#include <linux/interrupt.h> 101+#include <linux/mod_devicetable.h> 102+#include <linux/module.h> 103+#include <linux/platform_device.h> 104+#include <linux/iopoll.h> 105+#include <linux/io.h> 106+#include <linux/kernel.h> 107+ 108+#define CTRL 0x8 109+#define FLEXIO_CTRL_DOZEN_MASK 0x80000000 110+#define FLEXIO_CTRL_DOZEN(x) (((u32)(((u32)(x)) << 31)) & 0x80000000) 111+#define FLEXIO_CTRL_DBGE_MASK 0x40000000 112+#define FLEXIO_CTRL_DBGE(x) (((u32)(((u32)(x)) << 30)) & 0x40000000) 113+#define FLEXIO_CTRL_FASTACC_MASK 0x4 114+#define FLEXIO_CTRL_FASTACC(x) (((u32)(((u32)(x)) << 2)) & 0x4) 115+#define FLEXIO_CTRL_SWRST_MASK 0x2 116+#define FLEXIO_CTRL_SWRST(x) (((u32)(((u32)(x)) << 1)) & 0x2) 117+#define FLEXIO_CTRL_FLEXEN_MASK 0x1 118+#define FLEXIO_CTRL_FLEXEN(x) (((u32)(((u32)(x)) << 0)) & 0x1) 119+ 120+#define PIN 0xc 121+#define SHIFTSTAT 0x10 122+#define SHIFTERR 0x14 123+#define TIMSTAT 0x18 124+#define SHIFTSIEN 0x20 125+#define SHIFTEIEN 0x24 126+#define PINSTAT 0x50 127+#define PINREN 0x58 128+ 129+#define SHIFTCTL_0 0x80 130+#define SHIFTCTL_1 0x84 131+#define SHIFTCTL_TIMSEL_MASK 0x7000000 132+#define SHIFTCTL_TIMSEL(x) (((u32)(((u32)(x)) << 24)) & 0x7000000) 133+#define SHIFTCTL_TIMPOL_MASK 0x800000 134+#define SHIFTCTL_TIMPOL(x) (((u32)(((u32)(x)) << 23)) & 0x800000) 135+#define SHIFTCTL_PINCFG_MASK 0x30000 136+#define SHIFTCTL_PINCFG(x) (((u32)(((u32)(x)) << 16)) & 0x30000) 137+#define SHIFTCTL_PINSEL_MASK 0x1f00 138+#define SHIFTCTL_PINSEL(x) (((u32)(((u32)(x)) << 8)) & 0x1f00) 139+#define SHIFTCTL_PINPOL_MASK 0x80 140+#define SHIFTCTL_PINPOL(x) (((u32)(((u32)(x)) << 7)) & 0x80) 141+#define SHIFTCTL_SMOD_MASK 0x7 142+#define SHIFTCTL_SMOD(x) (((u32)(((u32)(x)) << 0)) & 0x7) 143+#define SHIFT_ON_POSEDGE 0x0 144+#define SHIFT_ON_NEGEDGE 0x1 145+#define SHIFTER_PIN_OUTPUT_DISABLE 0x0 146+#define SHIFTER_PIN_OPEN_DRAIN_OUTPUT 0x1 147+#define PIN_ACTIVE_HIGH 0x0 148+#define PIN_ACTIVE_LOW 0x1 149+#define SHIFTER_DISABLE 0x0 150+#define SHIFTER_RECEIVE 0x1 151+#define SHIFTER_TRANSMIT 0x2 152+ 153+#define SHIFTCFG_0 0x100 154+#define SHIFTCFG_1 0x104 155+#define SHIFTCFG_INSRC_MASK 0x100 156+#define SHIFTCFG_INSRC(x) (((u32)(((u32)(x)) << 8)) & 0x100) 157+#define SHIFTCFG_SSTOP_MASK 0x30 158+#define SHIFTCFG_SSTOP(x) (((u32)(((u32)(x)) << 4)) & 0x30) 159+#define SHIFTCFG_SSTART_MASK 0x3 160+#define SHIFTCFG_SSTART(x) (((u32)(((u32)(x)) << 0)) & 0x3) 161+#define INPUT_SRC_PIN 0x0 162+#define SSTOP_BIT_LOW 0x2 163+#define SSTOP_BIT_HIGH 0x3 164+#define SSTART_BIT_DISABLE 0X0 165+#define SSTART_BIT_LOW 0x2 166+ 167+#define SHIFTBUFBIS_1 0x284 168+#define SHIFTBUFBBS_0 0x380 169+ 170+#define TIMCTL_0 0x400 171+#define TIMCTL_1 0x404 172+#define TIMCTL_TRGSEL_MASK 0x3F000000 173+#define TIMCTL_TRGSEL(x) (((u32)(((u32)(x)) << 24)) & 0x3F000000) 174+#define TIMCTL_TRGPOL_MASK 0x800000 175+#define TIMCTL_TRGPOL(x) (((u32)(((u32)(x)) << 23)) & 0x800000) 176+#define TIMCTL_TRGSRC_MASK 0x400000 177+#define TIMCTL_TRGSRC(x) (((u32)(((u32)(x)) << 22)) & 0x400000) 178+#define TIMCTL_PINCFG_MASK 0x30000 179+#define TIMCTL_PINCFG(x) (((u32)(((u32)(x)) << 16)) & 0x30000) 180+#define TIMCTL_PINSEL_MASK 0x1f00 181+#define TIMCTL_PINSEL(x) (((u32)(((u32)(x)) << 8)) & 0x1f00) 182+#define TIMCTL_PINPOL_MASK 0x80 183+#define TIMCTL_PINPOL(x) (((u32)(((u32)(x)) << 7)) & 0x80) 184+#define TIMCTL_TIMOD_MASK 0x7 185+#define TIMCTL_TIMOD(x) (((u32)(((u32)(x)) << 0)) & 0x7) 186+#define TIMER_TRGSEL_SHIFTER(x) (((u32)(x) << 2U) | 0x1U) 187+#define TIMER_TRG_ACTIVE_LOW 0x1 188+#define TIMER_TRGSRC_INTER 0x1 189+#define TIMPIN_OUTPUT_DISABLE 0x0 190+#define TIMPIN_OPEN_DRAIN_OUTPUT 0x1 191+#define TIMPIN_ACTIVE_HIGH 0x0 192+#define TIMPIN_ACTIVE_LOW 0x1 193+#define TIMER_DISABLE 0x0 194+#define DUAL_8BIT_COUNTERS_BAUD 0x1 195+#define SINGLE_16BIT_COUNTER 0x3 196+ 197+#define TIMCFG_0 0x480 198+#define TIMCFG_1 0x484 199+#define TIMCFG_TIMOUT_MASK 0x3000000 200+#define TIMCFG_TIMOUT(x) (((u32)(((u32)(x)) << 24)) & 0x3000000) 201+#define TIMCFG_TIMDEC_MASK 0x700000 202+#define TIMCFG_TIMDEC(x) (((u32)(((u32)(x)) << 20)) & 0x700000) 203+#define TIMCFG_TIMRST_MASK 0x70000 204+#define TIMCFG_TIMRST(x) (((u32)(((u32)(x)) << 16)) & 0x70000) 205+#define TIMCFG_TIMDIS_MASK 0x7000 206+#define TIMCFG_TIMDIS(x) (((u32)(((u32)(x)) << 12)) & 0x7000) 207+#define TIMCFG_TIMENA_MASK 0x700 208+#define TIMCFG_TIMENA(x) (((u32)(((u32)(x)) << 8)) & 0x700) 209+#define TIMCFG_TSTOP_MASK 0x30 210+#define TIMCFG_TSTOP(x) (((u32)(((u32)(x)) << 4)) & 0x30) 211+#define TIMCFG_TSTART_MASK 0x2 212+#define TIMCFG_TSTART(x) (((u32)(((u32)(x)) << 1)) & 0x2) 213+#define TIMOUT_ONE_NOTAFFECT_BY_RESET 0x0 214+#define TIMOUT_ZERO_NOTAFFECT_BY_RESET 0x1 215+#define TIMDEC_FLEXIO_CLK 0x0 216+#define TIMDEC_PIN_INPUT 0x2 217+#define TIMRST_NEVER 0x0 218+#define TIMRST_TIMPIN_EQUAL_TIMOUTPUT 0x2 219+#define TIMDIS_TIMER_DISABLE 0x1 220+#define TIMDIS_TIMER_COMPARE 0x2 221+#define TIMDIS_PIN_EDGE 0x4 222+#define TIMENA_PREV_TIMENA 0X1 223+#define TIMENA_TRG_HIGH 0x2 224+#define TSTOP_BIT_DISABLE 0x0 225+#define TSTOP_BIT_ENABLE_TIMCMP 0x1 226+#define TSTOP_BIT_ENABLE_TIMDIS 0x2 227+#define TSTART_BIT_DISABLE 0x0 228+#define TSTART_BIT_ENABLE 0x1 229+ 230+#define TIMCMP_0 0x500 231+#define TIMCMP_1 0x504 232+ 233+#define TRANSMIT_STAT 0x1 234+#define RECEIVE_STAT 0x2 235+#define XFER_TIMEOUT 10000 236+ 237+struct flexio_control { 238+ bool dozen; 239+ bool dbge; 240+ bool fastacc; 241+ bool swrst; 242+ bool flexen; 243+}; 244+ 245+struct flexio_shifter_control { 246+ u8 timsel; 247+ u8 timpol; 248+ u8 pincfg; 249+ u8 pinsel; 250+ u8 pinpol; 251+ u8 smod; 252+}; 253+ 254+struct flexio_shifter_config { 255+ u8 pwidth; 256+ u8 sszie; 257+ u8 latst; 258+ u8 insrc; 259+ u8 sstop; 260+ u8 sstart; 261+}; 262+ 263+struct flexio_timer_control { 264+ u8 trgsel; 265+ u8 trgpol; 266+ u8 trgsrc; 267+ u8 pincfg; 268+ u8 pinsel; 269+ u8 pinpol; 270+ u8 timod; 271+}; 272+ 273+struct flexio_timer_config { 274+ u8 timout; 275+ u8 timdec; 276+ u8 timrst; 277+ u8 timdis; 278+ u8 timena; 279+ u8 tstop; 280+ u8 tstart; 281+}; 282+ 283+static void flexio_writel(void *base, u32 val, unsigned int reg) 284+{ 285+ writel_relaxed(val, base + reg); 286+} 287+ 288+static u32 flexio_readl(void *base, unsigned int reg) 289+{ 290+ return readl_relaxed(base + reg); 291+} 292+ 293+static void flexio_sw_reset(void *base, unsigned int reg) 294+{ 295+ u32 val = 0; 296+ 297+ val = flexio_readl(base, reg) | FLEXIO_CTRL_SWRST_MASK; 298+ flexio_writel(base, val, reg); 299+ 300+ flexio_writel(base, 0, reg); 301+} 302+ 303+static void flexio_get_default_ctrl(struct flexio_control *ctrl) 304+{ 305+ memset(ctrl, 0, sizeof(*ctrl)); 306+ 307+ ctrl->dozen = false; 308+ ctrl->dbge = true; 309+ ctrl->fastacc = false; 310+ ctrl->flexen = true; 311+} 312+ 313+static void flexio_setup_ctrl(void *base, struct flexio_control *ctrl, 314+ unsigned int reg) 315+{ 316+ u32 val = 0; 317+ 318+ val &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | 319+ FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); 320+ val |= (FLEXIO_CTRL_DBGE(ctrl->dbge) | 321+ FLEXIO_CTRL_FASTACC(ctrl->fastacc) | 322+ FLEXIO_CTRL_FLEXEN(ctrl->flexen)); 323+ 324+ if (!ctrl->dozen) 325+ val |= FLEXIO_CTRL_DOZEN_MASK; 326+ 327+ flexio_writel(base, val, reg); 328+} 329+ 330+static void flexio_setup_shiftctl(void *base, struct flexio_shifter_control *ctl, 331+ unsigned int reg) 332+{ 333+ u32 val = 0; 334+ 335+ val = SHIFTCTL_TIMSEL(ctl->timsel) | SHIFTCTL_TIMPOL(ctl->timpol) | 336+ SHIFTCTL_PINCFG(ctl->pincfg) | SHIFTCTL_PINSEL(ctl->pinsel) | 337+ SHIFTCTL_PINPOL(ctl->pinpol) | SHIFTCTL_SMOD(ctl->smod); 338+ 339+ flexio_writel(base, val, reg); 340+} 341+ 342+static void flexio_setup_shiftcfg(void *base, struct flexio_shifter_config *cfg, 343+ unsigned int reg) 344+{ 345+ u32 val = 0; 346+ 347+ val = SHIFTCFG_INSRC(cfg->insrc) | SHIFTCFG_SSTOP(cfg->sstop) | 348+ SHIFTCFG_SSTART(cfg->sstart); 349+ 350+ flexio_writel(base, val, reg); 351+} 352+ 353+static void flexio_setup_timerctl(void *base, struct flexio_timer_control *ctl, 354+ unsigned int reg) 355+{ 356+ u32 val = 0; 357+ 358+ val = TIMCTL_TRGSEL(ctl->trgsel) | TIMCTL_TRGPOL(ctl->trgpol) | 359+ TIMCTL_TRGSRC(ctl->trgsrc) | TIMCTL_PINCFG(ctl->pincfg) | 360+ TIMCTL_PINSEL(ctl->pinsel) | TIMCTL_PINPOL(ctl->pinpol) | 361+ TIMCTL_TIMOD(ctl->timod); 362+ 363+ flexio_writel(base, val, reg); 364+} 365+ 366+static void flexio_setup_timercfg(void *base, struct flexio_timer_config *cfg, 367+ unsigned int reg) 368+{ 369+ u32 val = 0; 370+ 371+ val = TIMCFG_TIMOUT(cfg->timout) | TIMCFG_TIMDEC(cfg->timdec) | 372+ TIMCFG_TIMRST(cfg->timrst) | TIMCFG_TIMDIS(cfg->timdis) | 373+ TIMCFG_TIMENA(cfg->timena) | TIMCFG_TSTOP(cfg->tstop) | 374+ TIMCFG_TSTART(cfg->tstart); 375+ 376+ flexio_writel(base, val, reg); 377+} 378+ 379+enum transfer_state { 380+ START_ADDRESS_WRITE, 381+ WRITE_DATA, 382+ WRITE_END, 383+ START_ADDRESS_READ, 384+ READ_NOT_LAST_DATA, 385+ READ_LAST_DATA, 386+ READ_END, 387+}; 388+ 389+enum stop_position { 390+ NOT_LAST_8_BIT, 391+ LAST_8_BIT, 392+}; 393+ 394+struct imx_flexio_i2c_master_dev { 395+ void __iomem *base; 396+ 397+ struct device *dev; 398+ struct clk *clk; 399+ struct i2c_adapter adapter; 400+ struct completion complete; 401+ enum transfer_state state; 402+ enum stop_position stop; 403+ 404+ spinlock_t lock; 405+ 406+ unsigned int irq; 407+ unsigned int baudrate; 408+ unsigned int src_clock; 409+ u8 shifters[2]; 410+ u8 timers[2]; 411+ u8 sda_pin; 412+ u8 scl_pin; 413+ u8 slave_addr; 414+ u8 *data; 415+ u16 len; 416+ 417+ bool need_check_ack; 418+ bool nack; 419+ bool read; 420+ bool repeated_start; 421+}; 422+ 423+enum shifter_flags { 424+ TX_EMPTY_F = BIT(0), 425+ RX_FULL_F = BIT(1), 426+ TX_ERR_F = BIT(2), 427+ RX_NAK_F = BIT(3), 428+}; 429+ 430+static void i2c_master_enable_ack(struct imx_flexio_i2c_master_dev *i2c_dev, 431+ bool enable) 432+{ 433+ void __iomem *base = i2c_dev->base; 434+ u32 cfg; 435+ 436+ cfg = flexio_readl(base, SHIFTCFG_0); 437+ cfg &= ~SHIFTCFG_SSTOP_MASK; 438+ if (enable) 439+ cfg |= SHIFTCFG_SSTOP(SSTOP_BIT_LOW); 440+ else 441+ cfg |= SHIFTCFG_SSTOP(SSTOP_BIT_HIGH); 442+ 443+ flexio_writel(base, cfg, SHIFTCFG_0); 444+} 445+ 446+static irqreturn_t imx_flexio_i2c_isr(int irq, void *dev_id) 447+{ 448+ struct imx_flexio_i2c_master_dev *i2c_dev = dev_id; 449+ void __iomem *base = i2c_dev->base; 450+ void __iomem *pinstat = i2c_dev->base + PINSTAT; 451+ u32 shiftstat, ack, val, ctl; 452+ 453+ shiftstat = flexio_readl(base, SHIFTSTAT); 454+ 455+ if (shiftstat & TRANSMIT_STAT) { 456+ switch (i2c_dev->state) { 457+ case START_ADDRESS_WRITE: 458+ flexio_writel(base, i2c_dev->slave_addr, SHIFTBUFBBS_0); 459+ 460+ if (i2c_dev->len > 0) 461+ i2c_dev->state = WRITE_DATA; 462+ else 463+ i2c_dev->state = WRITE_END; 464+ break; 465+ case WRITE_DATA: 466+ flexio_writel(base, *i2c_dev->data, SHIFTBUFBBS_0); 467+ i2c_dev->data++; 468+ i2c_dev->len--; 469+ 470+ if (!i2c_dev->len) 471+ i2c_dev->state = WRITE_END; 472+ break; 473+ case WRITE_END: 474+ if (i2c_dev->repeated_start) 475+ flexio_writel(base, 0xff, SHIFTBUFBBS_0); 476+ 477+ i2c_dev->stop = LAST_8_BIT; 478+ break; 479+ case START_ADDRESS_READ: 480+ flexio_writel(base, i2c_dev->slave_addr, SHIFTBUFBBS_0); 481+ 482+ if (i2c_dev->len > 1) 483+ i2c_dev->state = READ_NOT_LAST_DATA; 484+ else if (i2c_dev->len == 1) 485+ i2c_dev->state = READ_LAST_DATA; 486+ else if (i2c_dev->len == 0) 487+ i2c_dev->state = READ_END; 488+ break; 489+ case READ_NOT_LAST_DATA: 490+ flexio_writel(base, 0xff, SHIFTBUFBBS_0); 491+ break; 492+ case READ_LAST_DATA: 493+ i2c_master_enable_ack(i2c_dev, false); 494+ flexio_writel(base, 0xff, SHIFTBUFBBS_0); 495+ break; 496+ case READ_END: 497+ i2c_dev->stop = LAST_8_BIT; 498+ default: 499+ break; 500+ } 501+ } 502+ 503+ if (shiftstat & RECEIVE_STAT) { 504+ if (i2c_dev->need_check_ack) { 505+ ack = flexio_readl(base, SHIFTERR) & 2; 506+ if (!ack) { 507+ if (i2c_dev->stop == LAST_8_BIT) { 508+ flexio_writel(base, 0, SHIFTSIEN); 509+ complete(&i2c_dev->complete); 510+ } 511+ 512+ if (i2c_dev->read) { 513+ i2c_dev->need_check_ack = false; 514+ i2c_dev->read = false; 515+ flexio_readl(base, SHIFTBUFBIS_1); 516+ 517+ switch (i2c_dev->state) { 518+ case READ_NOT_LAST_DATA: 519+ i2c_master_enable_ack(i2c_dev, true); 520+ break; 521+ case READ_LAST_DATA: 522+ i2c_master_enable_ack(i2c_dev, false); 523+ i2c_dev->state = READ_END; 524+ break; 525+ case READ_END: 526+ default: 527+ flexio_writel(base, 0, SHIFTSIEN); 528+ complete(&i2c_dev->complete); 529+ break; 530+ } 531+ } 532+ } else { 533+ flexio_writel(base, 0, SHIFTSIEN); 534+ i2c_dev->nack = true; 535+ 536+ switch (i2c_dev->stop) { 537+ case NOT_LAST_8_BIT: 538+ goto stop; 539+ case LAST_8_BIT: 540+ flexio_writel(base, 0, SHIFTBUFBBS_0); 541+ complete(&i2c_dev->complete); 542+ break; 543+ default: 544+ complete(&i2c_dev->complete); 545+ break; 546+ } 547+ } 548+ 549+ flexio_readl(base, SHIFTBUFBIS_1); 550+ } else { 551+ *i2c_dev->data = flexio_readl(base, SHIFTBUFBIS_1); 552+ i2c_dev->data++; 553+ i2c_dev->len--; 554+ 555+ if (i2c_dev->len == 1) 556+ i2c_dev->state = READ_LAST_DATA; 557+ else if (i2c_dev->len == 0) { 558+ flexio_writel(base, 0, SHIFTBUFBBS_0); 559+ 560+ flexio_writel(base, 0, SHIFTSIEN); 561+ complete(&i2c_dev->complete); 562+ } 563+ } 564+ } 565+ 566+ return IRQ_HANDLED; 567+ 568+stop: 569+ /* generate STOP */ 570+ flexio_writel(base, 0, SHIFTBUFBBS_0); 571+ 572+ /* 573+ * Software should then wait for the next rising edge on SCL and then 574+ * disable both timers. 575+ */ 576+ flexio_writel(base, 1 << i2c_dev->scl_pin, PINREN); 577+ readl_relaxed_poll_timeout(pinstat, val, val & (1 << i2c_dev->scl_pin), 0, 1000); 578+ 579+ ctl = flexio_readl(base, TIMCTL_0); 580+ ctl &= ~TIMCTL_TIMOD_MASK; 581+ ctl |= TIMCTL_TIMOD(TIMER_DISABLE); 582+ flexio_writel(base, ctl, TIMCTL_0); 583+ 584+ ctl = flexio_readl(base, TIMCTL_1); 585+ ctl &= ~TIMCTL_TIMOD_MASK; 586+ ctl |= TIMCTL_TIMOD(TIMER_DISABLE); 587+ flexio_writel(base, ctl, TIMCTL_1); 588+ 589+ /* 590+ * The transmit shifter should then be disabled after waiting the setup 591+ * delay for a repeated START or STOP condition. 592+ */ 593+ udelay(10); 594+ ctl = flexio_readl(base, SHIFTCTL_0); 595+ ctl &= ~SHIFTCTL_PINCFG_MASK; 596+ ctl |= SHIFTCTL_PINCFG(SHIFTER_PIN_OUTPUT_DISABLE); 597+ ctl &= ~SHIFTCTL_SMOD_MASK; 598+ ctl |= SHIFTCTL_SMOD(SHIFTER_DISABLE); 599+ flexio_writel(base, ctl, SHIFTCTL_0); 600+ 601+ flexio_writel(base, 0, PINREN); 602+ flexio_writel(base, 1 << i2c_dev->scl_pin, PINSTAT); 603+ 604+ complete(&i2c_dev->complete); 605+ 606+ return IRQ_HANDLED; 607+} 608+ 609+static void clear_shifter_flags(struct imx_flexio_i2c_master_dev *i2c_dev, 610+ enum shifter_flags flags) 611+{ 612+ void __iomem *base = i2c_dev->base; 613+ u32 v = 1; 614+ u8 tx = i2c_dev->shifters[0], rx = i2c_dev->shifters[1]; 615+ 616+ /* 617+ * For SMOD = Transmit, the status flag is set when SHIFTBUF is empty or 618+ * when initially configured for SMOD=Transmit. 619+ * For SMOD = Receive, the status flag is set when SHIFTBUF is full, and 620+ * the shifter error flag is set when the received start or stop bit 621+ * does not match the expected value. 622+ */ 623+ if (flags & TX_EMPTY_F) 624+ flexio_writel(base, v << tx, SHIFTSTAT); 625+ if (flags & RX_FULL_F) 626+ flexio_writel(base, v << rx, SHIFTSTAT); 627+ if (flags & TX_ERR_F) 628+ flexio_writel(base, v << tx, SHIFTERR); 629+ if (flags & RX_NAK_F) 630+ flexio_writel(base, v << rx, SHIFTERR); 631+} 632+ 633+static void imx_flexio_init_hardware(struct imx_flexio_i2c_master_dev *i2c_dev) 634+{ 635+ void __iomem *base = i2c_dev->base; 636+ struct flexio_control ctrl; 637+ struct flexio_shifter_control shiftctl; 638+ struct flexio_shifter_config shiftcfg; 639+ struct flexio_timer_control timerctl; 640+ struct flexio_timer_config timercfg; 641+ u32 timercmp; 642+ 643+ flexio_sw_reset(base, CTRL); 644+ 645+ /* configure the shifter 0 as transmitter */ 646+ shiftcfg.insrc = INPUT_SRC_PIN; 647+ shiftcfg.sstop = SSTOP_BIT_HIGH; 648+ shiftcfg.sstart = SSTART_BIT_LOW; 649+ flexio_setup_shiftcfg(base, &shiftcfg, SHIFTCFG_0); 650+ 651+ shiftctl.timsel = i2c_dev->timers[1]; 652+ shiftctl.timpol = SHIFT_ON_POSEDGE; 653+ shiftctl.pincfg = SHIFTER_PIN_OPEN_DRAIN_OUTPUT; 654+ shiftctl.pinsel = i2c_dev->sda_pin; 655+ shiftctl.pinpol = PIN_ACTIVE_LOW; 656+ shiftctl.smod = SHIFTER_TRANSMIT; 657+ flexio_setup_shiftctl(base, &shiftctl, SHIFTCTL_0); 658+ 659+ /* configure the shifter 1 as receiver */ 660+ shiftcfg.insrc = INPUT_SRC_PIN; 661+ shiftcfg.sstop = SSTOP_BIT_LOW; 662+ shiftcfg.sstart = SSTART_BIT_DISABLE; 663+ flexio_setup_shiftcfg(base, &shiftcfg, SHIFTCFG_1); 664+ 665+ shiftctl.timsel = i2c_dev->timers[1]; 666+ shiftctl.timpol = SHIFT_ON_NEGEDGE; 667+ shiftctl.pincfg = SHIFTER_PIN_OUTPUT_DISABLE; 668+ shiftctl.pinsel = i2c_dev->sda_pin; 669+ shiftctl.pinpol = PIN_ACTIVE_HIGH; 670+ shiftctl.smod = SHIFTER_RECEIVE; 671+ flexio_setup_shiftctl(base, &shiftctl, SHIFTCTL_1); 672+ 673+ /* configure the timer 0 for the SCL and to trigger the timer 1 */ 674+ timercfg.timout = TIMOUT_ZERO_NOTAFFECT_BY_RESET; 675+ timercfg.timdec = TIMDEC_FLEXIO_CLK; 676+ timercfg.timrst = TIMRST_TIMPIN_EQUAL_TIMOUTPUT; 677+ timercfg.timdis = TIMDIS_TIMER_COMPARE; 678+ timercfg.timena = TIMENA_TRG_HIGH; 679+ timercfg.tstop = TSTOP_BIT_ENABLE_TIMDIS; 680+ timercfg.tstart = TSTART_BIT_ENABLE; 681+ flexio_setup_timercfg(base, &timercfg, TIMCFG_0); 682+ 683+ /* the baud rate divider equal to (CMP[7:0] + 1) * 2 */ 684+ timercmp = (u32)(i2c_dev->src_clock / i2c_dev->baudrate) / 2 - 1; 685+ flexio_writel(base, timercmp, TIMCMP_0); 686+ 687+ timerctl.trgsel = TIMER_TRGSEL_SHIFTER(i2c_dev->shifters[0]); 688+ timerctl.trgpol = TIMER_TRG_ACTIVE_LOW; 689+ timerctl.trgsrc = TIMER_TRGSRC_INTER; 690+ timerctl.pincfg = TIMPIN_OPEN_DRAIN_OUTPUT; 691+ timerctl.pinsel = i2c_dev->scl_pin; 692+ timerctl.pinpol = TIMPIN_ACTIVE_HIGH; 693+ timerctl.timod = DUAL_8BIT_COUNTERS_BAUD; 694+ flexio_setup_timerctl(base, &timerctl, TIMCTL_0); 695+ 696+ /* configure the timer 1 to control shifters */ 697+ timercfg.timout = TIMOUT_ONE_NOTAFFECT_BY_RESET; 698+ timercfg.timdec = TIMDEC_PIN_INPUT; 699+ timercfg.timrst = TIMRST_NEVER; 700+ timercfg.timdis = TIMDIS_TIMER_DISABLE; 701+ timercfg.timena = TIMENA_PREV_TIMENA; 702+ timercfg.tstop = TSTOP_BIT_ENABLE_TIMCMP; 703+ timercfg.tstart = TSTART_BIT_ENABLE; 704+ flexio_setup_timercfg(base, &timercfg, TIMCFG_1); 705+ 706+ /* the number of bits in each word equal to (CMP[15:0] + 1) / 2 */ 707+ timercmp = 8 * 2 - 1; 708+ flexio_writel(i2c_dev->base, timercmp, TIMCMP_1); 709+ 710+ timerctl.trgsel = TIMER_TRGSEL_SHIFTER(i2c_dev->shifters[0]); 711+ timerctl.trgpol = TIMER_TRG_ACTIVE_LOW; 712+ timerctl.trgsrc = TIMER_TRGSRC_INTER; 713+ timerctl.pincfg = TIMPIN_OUTPUT_DISABLE; 714+ timerctl.pinsel = i2c_dev->scl_pin; 715+ timerctl.pinpol = TIMPIN_ACTIVE_LOW; 716+ timerctl.timod = SINGLE_16BIT_COUNTER; 717+ flexio_setup_timerctl(base, &timerctl, TIMCTL_1); 718+ 719+ /* disable the shifter status interrupt and shifter error interrupt */ 720+ flexio_writel(base, 0, SHIFTSIEN); 721+ flexio_writel(base, 0, SHIFTEIEN); 722+ 723+ flexio_get_default_ctrl(&ctrl); 724+ flexio_setup_ctrl(base, &ctrl, CTRL); 725+} 726+ 727+static int i2c_bus_busy(struct imx_flexio_i2c_master_dev *i2c_dev) 728+{ 729+ unsigned int i, mask; 730+ void __iomem *base = i2c_dev->base; 731+ 732+ /* 733+ * If in certain loops the SDA/SCL is continuously pulled down, then 734+ * return bus busy status. 735+ */ 736+ for (i = 0; i < 100; i++) { 737+ mask = 1 << i2c_dev->sda_pin | 1 << i2c_dev->scl_pin; 738+ 739+ if ((flexio_readl(base, PIN) & mask) == mask) 740+ return 0; 741+ } 742+ 743+ return -EBUSY; 744+} 745+ 746+static int setup_xfer_count(struct imx_flexio_i2c_master_dev *i2c_dev, 747+ u32 xfer_len) 748+{ 749+ void __iomem *base = i2c_dev->base; 750+ u32 cmp, cfg; 751+ 752+ if (xfer_len > ((0xff - 1) / (16 + 1 + 1))) { 753+ dev_err(i2c_dev->dev, "more than 14 bytes to be transferred\n"); 754+ return -EINVAL; 755+ } 756+ 757+ /* configure the number of shift clock edges in the transfer */ 758+ cmp = flexio_readl(base, TIMCMP_0); 759+ cmp &= 0x00ff; 760+ cmp |= (xfer_len * 18 + 1) << 8; 761+ flexio_writel(base, cmp, TIMCMP_0); 762+ 763+ cfg = flexio_readl(base, TIMCFG_0); 764+ cfg &= ~TIMCFG_TIMDIS_MASK; 765+ cfg |= TIMCFG_TIMDIS(TIMDIS_TIMER_COMPARE); 766+ flexio_writel(base, cfg, TIMCFG_0); 767+ 768+ return 0; 769+} 770+ 771+static int i2c_master_write(struct imx_flexio_i2c_master_dev *i2c_dev, 772+ struct i2c_msg *msg) 773+{ 774+ void __iomem *base = i2c_dev->base; 775+ void __iomem *timstat = base + TIMSTAT; 776+ int timeout, val; 777+ 778+ i2c_dev->state = START_ADDRESS_WRITE; 779+ if (msg->len) 780+ i2c_dev->stop = NOT_LAST_8_BIT; 781+ else 782+ i2c_dev->stop = LAST_8_BIT; 783+ i2c_dev->need_check_ack = true; 784+ 785+ i2c_dev->slave_addr = i2c_8bit_addr_from_msg(msg); 786+ i2c_dev->data = msg->buf; 787+ i2c_dev->len = msg->len; 788+ 789+ flexio_writel(base, 3, SHIFTSIEN); 790+ 791+ timeout = wait_for_completion_timeout(&i2c_dev->complete, XFER_TIMEOUT); 792+ if (timeout) { 793+ if (i2c_dev->nack) 794+ return -EIO; 795+ } else { 796+ return -EIO; 797+ } 798+ reinit_completion(&i2c_dev->complete); 799+ 800+ i2c_dev->nack = false; 801+ flexio_writel(base, 0, SHIFTSIEN); 802+ 803+ readl_relaxed_poll_timeout(timstat, val, val & 1, 0, 1000); 804+ flexio_writel(base, 1, TIMSTAT); 805+ 806+ return 0; 807+} 808+ 809+static int i2c_master_read(struct imx_flexio_i2c_master_dev *i2c_dev, 810+ struct i2c_msg *msg) 811+{ 812+ void __iomem *base = i2c_dev->base; 813+ void __iomem *timstat = base + TIMSTAT; 814+ int timeout, val; 815+ 816+ clear_shifter_flags(i2c_dev, RX_FULL_F); 817+ 818+ i2c_dev->state = START_ADDRESS_READ; 819+ if (msg->len) 820+ i2c_dev->stop = NOT_LAST_8_BIT; 821+ else 822+ i2c_dev->stop = LAST_8_BIT; 823+ i2c_dev->need_check_ack = true; 824+ i2c_dev->read = true; 825+ 826+ i2c_dev->slave_addr = i2c_8bit_addr_from_msg(msg); 827+ i2c_dev->data = msg->buf; 828+ i2c_dev->len = msg->len; 829+ 830+ flexio_writel(base, 3, SHIFTSIEN); 831+ 832+ timeout = wait_for_completion_timeout(&i2c_dev->complete, XFER_TIMEOUT); 833+ if (timeout) { 834+ if (i2c_dev->nack) 835+ return -EIO; 836+ } else { 837+ return -EIO; 838+ } 839+ reinit_completion(&i2c_dev->complete); 840+ 841+ i2c_dev->nack = false; 842+ flexio_writel(base, 0, SHIFTSIEN); 843+ 844+ readl_relaxed_poll_timeout(timstat, val, val & 1, 0, 1000); 845+ flexio_writel(base, 1, TIMSTAT); 846+ 847+ return 0; 848+} 849+ 850+static int xfer_msg(struct imx_flexio_i2c_master_dev *i2c_dev, struct i2c_msg *msg) 851+{ 852+ void __iomem *base = i2c_dev->base; 853+ void __iomem *shiftstat = base + SHIFTSTAT; 854+ u32 xfer_len, val; 855+ bool msg_read = !!(msg->flags & I2C_M_RD); 856+ int err; 857+ 858+ xfer_len = msg->len + 1; 859+ 860+ /* 861+ * Sets the number of bytes to be transferred from a start signal to a 862+ * stop signal. Timer 0 is used to generate SCL output and to trigger 863+ * timer 1. 864+ */ 865+ if (setup_xfer_count(i2c_dev, xfer_len)) 866+ return -EINVAL; 867+ 868+ err = readl_relaxed_poll_timeout(shiftstat, val, val & 1, 0, 1000); 869+ if (err) { 870+ dev_err(i2c_dev->dev, "wait transmit SHIFTBUF empty timeout\n"); 871+ return err; 872+ } 873+ 874+ if (!msg_read) 875+ err = i2c_master_write(i2c_dev, msg); 876+ else 877+ err = i2c_master_read(i2c_dev, msg); 878+ if (err) 879+ return err; 880+ 881+ return 0; 882+} 883+ 884+static int imx_flexio_i2c_master_xfer(struct i2c_adapter *adap, 885+ struct i2c_msg msgs[], int num) 886+{ 887+ struct imx_flexio_i2c_master_dev *i2c_dev = i2c_get_adapdata(adap); 888+ void __iomem *base = i2c_dev->base; 889+ u32 ctl; 890+ int i, err; 891+ 892+ if (i2c_dev->nack) { 893+ ctl = flexio_readl(base, SHIFTCTL_0); 894+ ctl &= ~SHIFTCTL_PINCFG_MASK; 895+ ctl |= SHIFTCTL_PINCFG(SHIFTER_PIN_OPEN_DRAIN_OUTPUT); 896+ ctl &= ~SHIFTCTL_SMOD_MASK; 897+ ctl |= SHIFTCTL_SMOD(SHIFTER_TRANSMIT); 898+ flexio_writel(base, ctl, SHIFTCTL_0); 899+ 900+ ctl = flexio_readl(base, TIMCTL_0); 901+ ctl &= ~TIMCTL_TIMOD_MASK; 902+ ctl |= TIMCTL_TIMOD(DUAL_8BIT_COUNTERS_BAUD); 903+ flexio_writel(base, ctl, TIMCTL_0); 904+ 905+ ctl = flexio_readl(base, TIMCTL_1); 906+ ctl &= ~TIMCTL_TIMOD_MASK; 907+ ctl |= TIMCTL_TIMOD(SINGLE_16BIT_COUNTER); 908+ flexio_writel(base, ctl, TIMCTL_1); 909+ } 910+ i2c_dev->nack = false; 911+ 912+ i2c_dev->repeated_start = false; 913+ if (num > 1) 914+ i2c_dev->repeated_start = true; 915+ 916+ clear_shifter_flags(i2c_dev, RX_FULL_F | RX_NAK_F); 917+ 918+ err = i2c_bus_busy(i2c_dev); 919+ if (err) { 920+ dev_dbg(i2c_dev->dev, "SDA/SCL is continuously pulled down\n"); 921+ 922+ imx_flexio_init_hardware(i2c_dev); 923+ clear_shifter_flags(i2c_dev, RX_FULL_F | RX_NAK_F); 924+ } 925+ 926+ for (i = 0; i < num; i++) { 927+ err = xfer_msg(i2c_dev, &msgs[i]); 928+ if (err) 929+ return err; 930+ } 931+ 932+ return (err < 0) ? err : num; 933+} 934+ 935+static int imx_flexio_i2c_master_xfer_atomic(struct i2c_adapter *adap, 936+ struct i2c_msg msgs[], int num) 937+{ 938+ return 0; 939+} 940+ 941+static u32 imx_flexio_i2c_master_func(struct i2c_adapter *adap) 942+{ 943+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 944+} 945+ 946+static const struct i2c_algorithm imx_flexio_i2c_master_algo = { 947+ .master_xfer = imx_flexio_i2c_master_xfer, 948+ .master_xfer_atomic = imx_flexio_i2c_master_xfer_atomic, 949+ .functionality = imx_flexio_i2c_master_func, 950+}; 951+ 952+static int imx_flexio_i2c_issue_bus_clear(struct i2c_adapter *adap) 953+{ 954+ return 0; 955+} 956+ 957+static struct i2c_bus_recovery_info imx_flexio_i2c_recovery_info = { 958+ .recover_bus = imx_flexio_i2c_issue_bus_clear, 959+}; 960+ 961+static int imx_flexio_i2c_master_probe(struct platform_device *pdev) 962+{ 963+ struct imx_flexio_i2c_master_dev *i2c_dev; 964+ struct resource *res; 965+ int err; 966+ 967+ i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 968+ if (!i2c_dev) 969+ return -ENOMEM; 970+ 971+ platform_set_drvdata(pdev, i2c_dev); 972+ 973+ i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 974+ if (IS_ERR(i2c_dev->base)) 975+ return PTR_ERR(i2c_dev->base); 976+ 977+ i2c_dev->dev = &pdev->dev; 978+ 979+ err = platform_get_irq(pdev, 0); 980+ if (err < 0) 981+ return err; 982+ i2c_dev->irq = err; 983+ 984+ err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, imx_flexio_i2c_isr, 985+ IRQF_NO_SUSPEND, dev_name(i2c_dev->dev), 986+ i2c_dev); 987+ if (err) 988+ return err; 989+ 990+ i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 991+ if (IS_ERR(i2c_dev->clk)) { 992+ dev_err(&pdev->dev, "missing imx flexio i2c master clock\n"); 993+ return PTR_ERR(i2c_dev->clk); 994+ } 995+ 996+ err = clk_prepare_enable(i2c_dev->clk); 997+ if (err) { 998+ dev_err(i2c_dev->dev, "failed to enable imx flexio i2c master clock: %d\n", err); 999+ return err; 1000+ } 1001+ 1002+ /* hardware configuration */ 1003+ err = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &i2c_dev->baudrate); 1004+ if (err < 0) { 1005+ dev_err(i2c_dev->dev, "no clock-frequency found\n"); 1006+ return err; 1007+ } 1008+ i2c_dev->src_clock = clk_get_rate(i2c_dev->clk); 1009+ i2c_dev->shifters[0] = 0; 1010+ i2c_dev->shifters[1] = 1; 1011+ i2c_dev->timers[0] = 0; 1012+ i2c_dev->timers[1] = 1; 1013+ err = of_property_read_u8(pdev->dev.of_node, "sda", &i2c_dev->sda_pin); 1014+ if (err < 0) { 1015+ dev_err(i2c_dev->dev, "no sda property found\n"); 1016+ return err; 1017+ } 1018+ err = of_property_read_u8(pdev->dev.of_node, "scl", &i2c_dev->scl_pin); 1019+ if (err < 0) { 1020+ dev_err(i2c_dev->dev, "no scl property found\n"); 1021+ return err; 1022+ } 1023+ imx_flexio_init_hardware(i2c_dev); 1024+ 1025+ i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1026+ i2c_dev->adapter.owner = THIS_MODULE; 1027+ i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1028+ i2c_dev->adapter.algo = &imx_flexio_i2c_master_algo; 1029+ i2c_dev->adapter.timeout = 600; 1030+ i2c_dev->adapter.retries = 1; 1031+ i2c_dev->adapter.dev.parent = i2c_dev->dev; 1032+ i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; 1033+ i2c_dev->adapter.nr = pdev->id; 1034+ i2c_dev->adapter.bus_recovery_info = &imx_flexio_i2c_recovery_info; 1035+ 1036+ strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), 1037+ sizeof(i2c_dev->adapter.name)); 1038+ 1039+ init_completion(&i2c_dev->complete); 1040+ spin_lock_init(&i2c_dev->lock); 1041+ 1042+ err = i2c_add_adapter(&i2c_dev->adapter); 1043+ if (err) 1044+ goto release_clock; 1045+ 1046+ return 0; 1047+ 1048+release_clock: 1049+ clk_disable(i2c_dev->clk); 1050+ 1051+ return err; 1052+} 1053+ 1054+static int imx_flexio_i2c_master_remove(struct platform_device *pdev) 1055+{ 1056+ struct imx_flexio_i2c_master_dev *i2c_dev = platform_get_drvdata(pdev); 1057+ 1058+ i2c_del_adapter(&i2c_dev->adapter); 1059+ clk_disable(i2c_dev->clk); 1060+ return 0; 1061+} 1062+ 1063+static const struct of_device_id imx_flexio_i2c_master_of_match[] = { 1064+ { .compatible = "imx,flexio_i2c_master", }, 1065+ {}, 1066+}; 1067+MODULE_DEVICE_TABLE(of, imx_flexio_i2c_master_of_match); 1068+ 1069+static struct platform_driver imx_flexio_i2c_master_driver = { 1070+ .probe = imx_flexio_i2c_master_probe, 1071+ .remove = imx_flexio_i2c_master_remove, 1072+ .driver = { 1073+ .name = "imx-flexio-i2c-master", 1074+ .of_match_table = imx_flexio_i2c_master_of_match, 1075+ }, 1076+}; 1077+module_platform_driver(imx_flexio_i2c_master_driver); 1078+ 1079+MODULE_DESCRIPTION("NXP I.MX FlexIO I2C Master driver"); 1080+MODULE_AUTHOR("Alice Guo <alice.guo@nxp.com>"); 1081+MODULE_LICENSE("GPL v2"); 1082diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c 1083index 8b9ba055c..9b24ff253 100644 1084--- a/drivers/i2c/busses/i2c-imx-lpi2c.c 1085+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c 1086@@ -8,6 +8,8 @@ 1087 #include <linux/clk.h> 1088 #include <linux/completion.h> 1089 #include <linux/delay.h> 1090+#include <linux/dmaengine.h> 1091+#include <linux/dma-mapping.h> 1092 #include <linux/err.h> 1093 #include <linux/errno.h> 1094 #include <linux/i2c.h> 1095@@ -18,6 +20,7 @@ 1096 #include <linux/module.h> 1097 #include <linux/of.h> 1098 #include <linux/of_device.h> 1099+#include <linux/of_gpio.h> 1100 #include <linux/pinctrl/consumer.h> 1101 #include <linux/platform_device.h> 1102 #include <linux/pm_runtime.h> 1103@@ -30,6 +33,7 @@ 1104 #define LPI2C_MCR 0x10 /* i2c contrl register */ 1105 #define LPI2C_MSR 0x14 /* i2c status register */ 1106 #define LPI2C_MIER 0x18 /* i2c interrupt enable */ 1107+#define LPI2C_MDER 0x1C /* i2c DMA enable */ 1108 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ 1109 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ 1110 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ 1111@@ -71,18 +75,22 @@ 1112 #define MCFGR1_AUTOSTOP BIT(8) 1113 #define MCFGR1_IGNACK BIT(9) 1114 #define MRDR_RXEMPTY BIT(14) 1115+#define MDER_TDDE BIT(0) 1116+#define MDER_RDDE BIT(1) 1117 1118-#define I2C_CLK_RATIO 2 1119+#define I2C_CLK_RATIO 24 / 59 1120 #define CHUNK_DATA 256 1121 1122-#define I2C_PM_TIMEOUT 10 /* ms */ 1123+#define I2C_PM_TIMEOUT 1000 /* ms */ 1124+#define I2C_DMA_THRESHOLD 16 /* bytes */ 1125+#define I2C_USE_PIO (-150) 1126 1127 enum lpi2c_imx_mode { 1128- STANDARD, /* 100+Kbps */ 1129- FAST, /* 400+Kbps */ 1130- FAST_PLUS, /* 1.0+Mbps */ 1131- HS, /* 3.4+Mbps */ 1132- ULTRA_FAST, /* 5.0+Mbps */ 1133+ STANDARD, /* <=100Kbps */ 1134+ FAST, /* <=400Kbps */ 1135+ FAST_PLUS, /* <=1.0Mbps */ 1136+ HS, /* <=3.4Mbps */ 1137+ ULTRA_FAST, /* <=5.0Mbps */ 1138 }; 1139 1140 enum lpi2c_imx_pincfg { 1141@@ -94,7 +102,10 @@ enum lpi2c_imx_pincfg { 1142 1143 struct lpi2c_imx_struct { 1144 struct i2c_adapter adapter; 1145- struct clk *clk; 1146+ resource_size_t phy_addr; 1147+ int irq; 1148+ struct clk *clk_per; 1149+ struct clk *clk_ipg; 1150 void __iomem *base; 1151 __u8 *rx_buf; 1152 __u8 *tx_buf; 1153@@ -106,6 +117,22 @@ struct lpi2c_imx_struct { 1154 unsigned int txfifosize; 1155 unsigned int rxfifosize; 1156 enum lpi2c_imx_mode mode; 1157+ 1158+ struct i2c_bus_recovery_info rinfo; 1159+ struct pinctrl *pinctrl; 1160+ struct pinctrl_state *pinctrl_pins_default; 1161+ struct pinctrl_state *pinctrl_pins_gpio; 1162+ 1163+ bool can_use_dma; 1164+ bool using_dma; 1165+ bool xferred; 1166+ struct i2c_msg *msg; 1167+ dma_addr_t dma_addr; 1168+ struct dma_chan *dma_tx; 1169+ struct dma_chan *dma_rx; 1170+ enum dma_data_direction dma_direction; 1171+ u8 *dma_buf; 1172+ unsigned int dma_len; 1173 }; 1174 1175 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, 1176@@ -133,6 +160,8 @@ static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx) 1177 1178 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 1179 dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n"); 1180+ if (lpi2c_imx->adapter.bus_recovery_info) 1181+ i2c_recover_bus(&lpi2c_imx->adapter); 1182 return -ETIMEDOUT; 1183 } 1184 schedule(); 1185@@ -146,13 +175,13 @@ static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx) 1186 unsigned int bitrate = lpi2c_imx->bitrate; 1187 enum lpi2c_imx_mode mode; 1188 1189- if (bitrate < I2C_MAX_FAST_MODE_FREQ) 1190+ if (bitrate <= I2C_MAX_STANDARD_MODE_FREQ) 1191 mode = STANDARD; 1192- else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ) 1193+ else if (bitrate <= I2C_MAX_FAST_MODE_FREQ) 1194 mode = FAST; 1195- else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ) 1196+ else if (bitrate <= I2C_MAX_FAST_MODE_PLUS_FREQ) 1197 mode = FAST_PLUS; 1198- else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ) 1199+ else if (bitrate <= I2C_MAX_HIGH_SPEED_MODE_FREQ) 1200 mode = HS; 1201 else 1202 mode = ULTRA_FAST; 1203@@ -190,6 +219,8 @@ static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) 1204 1205 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 1206 dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n"); 1207+ if (lpi2c_imx->adapter.bus_recovery_info) 1208+ i2c_recover_bus(&lpi2c_imx->adapter); 1209 break; 1210 } 1211 schedule(); 1212@@ -197,17 +228,23 @@ static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) 1213 } while (1); 1214 } 1215 1216-/* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ 1217+/* CLKLO = (1 - I2C_CLK_RATIO) * clk_cycle, SETHOLD = CLKHI, DATAVD = CLKHI/2 1218+ CLKHI = I2C_CLK_RATIO * clk_cycle */ 1219 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) 1220 { 1221- u8 prescale, filt, sethold, clkhi, clklo, datavd; 1222- unsigned int clk_rate, clk_cycle; 1223+ u8 prescale, filt, sethold, datavd; 1224+ unsigned int clk_rate, clk_cycle, clkhi, clklo; 1225 enum lpi2c_imx_pincfg pincfg; 1226 unsigned int temp; 1227 1228 lpi2c_imx_set_mode(lpi2c_imx); 1229 1230- clk_rate = clk_get_rate(lpi2c_imx->clk); 1231+ clk_rate = clk_get_rate(lpi2c_imx->clk_per); 1232+ if (!clk_rate) { 1233+ dev_dbg(&lpi2c_imx->adapter.dev, "clk_per rate is 0\n"); 1234+ return -EINVAL; 1235+ } 1236+ 1237 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST) 1238 filt = 0; 1239 else 1240@@ -215,8 +252,8 @@ static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) 1241 1242 for (prescale = 0; prescale <= 7; prescale++) { 1243 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate) 1244- - 3 - (filt >> 1); 1245- clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1); 1246+ - (2 + filt) / (1 << prescale); 1247+ clkhi = clk_cycle * I2C_CLK_RATIO; 1248 clklo = clk_cycle - clkhi; 1249 if (clklo < 64) 1250 break; 1251@@ -271,6 +308,9 @@ static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx) 1252 if (ret) 1253 goto rpm_put; 1254 1255+ if (lpi2c_imx->can_use_dma) 1256+ writel(MDER_TDDE | MDER_RDDE, lpi2c_imx->base + LPI2C_MDER); 1257+ 1258 temp = readl(lpi2c_imx->base + LPI2C_MCR); 1259 temp |= MCR_MEN; 1260 writel(temp, lpi2c_imx->base + LPI2C_MCR); 1261@@ -322,6 +362,8 @@ static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx) 1262 1263 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 1264 dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n"); 1265+ if (lpi2c_imx->adapter.bus_recovery_info) 1266+ i2c_recover_bus(&lpi2c_imx->adapter); 1267 return -ETIMEDOUT; 1268 } 1269 schedule(); 1270@@ -442,6 +484,154 @@ static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx, 1271 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); 1272 } 1273 1274+static void lpi2c_dma_unmap(struct lpi2c_imx_struct *lpi2c_imx) 1275+{ 1276+ struct dma_chan *chan = lpi2c_imx->dma_direction == DMA_FROM_DEVICE 1277+ ? lpi2c_imx->dma_rx : lpi2c_imx->dma_tx; 1278+ 1279+ dma_unmap_single(chan->device->dev, lpi2c_imx->dma_addr, 1280+ lpi2c_imx->dma_len, lpi2c_imx->dma_direction); 1281+ 1282+ lpi2c_imx->dma_direction = DMA_NONE; 1283+} 1284+ 1285+static void lpi2c_cleanup_dma(struct lpi2c_imx_struct *lpi2c_imx) 1286+{ 1287+ if (lpi2c_imx->dma_direction == DMA_NONE) 1288+ return; 1289+ else if (lpi2c_imx->dma_direction == DMA_FROM_DEVICE) 1290+ dmaengine_terminate_all(lpi2c_imx->dma_rx); 1291+ else if (lpi2c_imx->dma_direction == DMA_TO_DEVICE) 1292+ dmaengine_terminate_all(lpi2c_imx->dma_tx); 1293+ 1294+ lpi2c_dma_unmap(lpi2c_imx); 1295+} 1296+ 1297+static void lpi2c_dma_callback(void *data) 1298+{ 1299+ struct lpi2c_imx_struct *lpi2c_imx = (struct lpi2c_imx_struct *)data; 1300+ 1301+ lpi2c_dma_unmap(lpi2c_imx); 1302+ writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); 1303+ lpi2c_imx->xferred = true; 1304+ 1305+ complete(&lpi2c_imx->complete); 1306+} 1307+ 1308+static int lpi2c_dma_submit(struct lpi2c_imx_struct *lpi2c_imx, 1309+ struct i2c_msg *msg) 1310+{ 1311+ bool read = msg->flags & I2C_M_RD; 1312+ enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 1313+ struct dma_chan *chan = read ? lpi2c_imx->dma_rx : lpi2c_imx->dma_tx; 1314+ struct dma_async_tx_descriptor *txdesc; 1315+ dma_cookie_t cookie; 1316+ 1317+ lpi2c_imx->dma_len = read ? msg->len - 1 : msg->len; 1318+ lpi2c_imx->msg = msg; 1319+ lpi2c_imx->dma_direction = dir; 1320+ 1321+ if (IS_ERR(chan)) 1322+ return PTR_ERR(chan); 1323+ 1324+ lpi2c_imx->dma_addr = dma_map_single(chan->device->dev, 1325+ lpi2c_imx->dma_buf, 1326+ lpi2c_imx->dma_len, dir); 1327+ if (dma_mapping_error(chan->device->dev, lpi2c_imx->dma_addr)) { 1328+ dev_err(&lpi2c_imx->adapter.dev, "dma map failed, use pio\n"); 1329+ return -EINVAL; 1330+ } 1331+ 1332+ txdesc = dmaengine_prep_slave_single(chan, lpi2c_imx->dma_addr, 1333+ lpi2c_imx->dma_len, read ? 1334+ DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 1335+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1336+ if (!txdesc) { 1337+ dev_err(&lpi2c_imx->adapter.dev, "dma prep slave sg failed, use pio\n"); 1338+ lpi2c_cleanup_dma(lpi2c_imx); 1339+ return -EINVAL; 1340+ } 1341+ 1342+ reinit_completion(&lpi2c_imx->complete); 1343+ txdesc->callback = lpi2c_dma_callback; 1344+ txdesc->callback_param = (void *)lpi2c_imx; 1345+ 1346+ cookie = dmaengine_submit(txdesc); 1347+ if (dma_submit_error(cookie)) { 1348+ dev_err(&lpi2c_imx->adapter.dev, "submitting dma failed, use pio\n"); 1349+ lpi2c_cleanup_dma(lpi2c_imx); 1350+ return -EINVAL; 1351+ } 1352+ 1353+ lpi2c_imx_intctrl(lpi2c_imx, MIER_NDIE); 1354+ 1355+ dma_async_issue_pending(chan); 1356+ 1357+ return 0; 1358+} 1359+ 1360+static bool is_use_dma(struct lpi2c_imx_struct *lpi2c_imx, struct i2c_msg *msg) 1361+{ 1362+ if (!lpi2c_imx->can_use_dma) 1363+ return false; 1364+ 1365+ if (msg->len < I2C_DMA_THRESHOLD) 1366+ return false; 1367+ 1368+ return true; 1369+} 1370+ 1371+static int lpi2c_imx_push_rx_cmd(struct lpi2c_imx_struct *lpi2c_imx, 1372+ struct i2c_msg *msg) 1373+{ 1374+ unsigned int temp, rx_remain; 1375+ unsigned long orig_jiffies = jiffies; 1376+ 1377+ if ((msg->flags & I2C_M_RD)) { 1378+ rx_remain = msg->len; 1379+ do { 1380+ temp = rx_remain > CHUNK_DATA ? 1381+ CHUNK_DATA - 1 : rx_remain - 1; 1382+ temp |= (RECV_DATA << 8); 1383+ while ((readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff) > 2) { 1384+ if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(1000))) { 1385+ dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n"); 1386+ if (lpi2c_imx->adapter.bus_recovery_info) 1387+ i2c_recover_bus(&lpi2c_imx->adapter); 1388+ return -ETIMEDOUT; 1389+ } 1390+ schedule(); 1391+ } 1392+ writel(temp, lpi2c_imx->base + LPI2C_MTDR); 1393+ rx_remain = rx_remain - (temp & 0xff) - 1; 1394+ } while (rx_remain > 0); 1395+ } 1396+ 1397+ return 0; 1398+} 1399+ 1400+static int lpi2c_dma_xfer(struct lpi2c_imx_struct *lpi2c_imx, 1401+ struct i2c_msg *msg) 1402+{ 1403+ int result; 1404+ 1405+ result = lpi2c_dma_submit(lpi2c_imx, msg); 1406+ if (!result) { 1407+ result = lpi2c_imx_push_rx_cmd(lpi2c_imx, msg); 1408+ if (result) 1409+ return result; 1410+ result = lpi2c_imx_msg_complete(lpi2c_imx); 1411+ return result; 1412+ } 1413+ 1414+ /* DMA xfer failed, try to use PIO, clean up dma things */ 1415+ i2c_put_dma_safe_msg_buf(lpi2c_imx->dma_buf, lpi2c_imx->msg, 1416+ lpi2c_imx->xferred); 1417+ lpi2c_cleanup_dma(lpi2c_imx); 1418+ 1419+ return I2C_USE_PIO; 1420+} 1421+ 1422 static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 1423 struct i2c_msg *msgs, int num) 1424 { 1425@@ -454,6 +644,9 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 1426 return result; 1427 1428 for (i = 0; i < num; i++) { 1429+ lpi2c_imx->xferred = false; 1430+ lpi2c_imx->using_dma = false; 1431+ 1432 result = lpi2c_imx_start(lpi2c_imx, &msgs[i]); 1433 if (result) 1434 goto disable; 1435@@ -462,9 +655,24 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 1436 if (num == 1 && msgs[0].len == 0) 1437 goto stop; 1438 1439+ if (is_use_dma(lpi2c_imx, &msgs[i])) { 1440+ lpi2c_imx->using_dma = true; 1441+ 1442+ writel(0x1, lpi2c_imx->base + LPI2C_MFCR); 1443+ 1444+ lpi2c_imx->dma_buf = i2c_get_dma_safe_msg_buf(&msgs[i], 1445+ I2C_DMA_THRESHOLD); 1446+ if (lpi2c_imx->dma_buf) { 1447+ result = lpi2c_dma_xfer(lpi2c_imx, &msgs[i]); 1448+ if (result != I2C_USE_PIO) 1449+ goto stop; 1450+ } 1451+ } 1452+ 1453+ lpi2c_imx->using_dma = false; 1454 lpi2c_imx->delivered = 0; 1455 lpi2c_imx->msglen = msgs[i].len; 1456- init_completion(&lpi2c_imx->complete); 1457+ reinit_completion(&lpi2c_imx->complete); 1458 1459 if (msgs[i].flags & I2C_M_RD) 1460 lpi2c_imx_read(lpi2c_imx, &msgs[i]); 1461@@ -483,7 +691,16 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 1462 } 1463 1464 stop: 1465- lpi2c_imx_stop(lpi2c_imx); 1466+ if (!lpi2c_imx->using_dma) 1467+ lpi2c_imx_stop(lpi2c_imx); 1468+ else { 1469+ i2c_put_dma_safe_msg_buf(lpi2c_imx->dma_buf, lpi2c_imx->msg, 1470+ lpi2c_imx->xferred); 1471+ if (result) { 1472+ lpi2c_cleanup_dma(lpi2c_imx); 1473+ writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); 1474+ } 1475+ } 1476 1477 temp = readl(lpi2c_imx->base + LPI2C_MSR); 1478 if ((temp & MSR_NDF) && !result) 1479@@ -507,18 +724,89 @@ static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) 1480 lpi2c_imx_intctrl(lpi2c_imx, 0); 1481 temp = readl(lpi2c_imx->base + LPI2C_MSR); 1482 1483+ if (temp & MSR_NDF) { 1484+ if (lpi2c_imx->using_dma) { 1485+ lpi2c_cleanup_dma(lpi2c_imx); 1486+ writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR); 1487+ } 1488+ complete(&lpi2c_imx->complete); 1489+ goto ret; 1490+ } 1491+ 1492 if (temp & MSR_RDF) 1493 lpi2c_imx_read_rxfifo(lpi2c_imx); 1494- 1495- if (temp & MSR_TDF) 1496+ else if (temp & MSR_TDF) 1497 lpi2c_imx_write_txfifo(lpi2c_imx); 1498 1499- if (temp & MSR_NDF) 1500- complete(&lpi2c_imx->complete); 1501- 1502+ret: 1503 return IRQ_HANDLED; 1504 } 1505 1506+static void lpi2c_imx_prepare_recovery(struct i2c_adapter *adap) 1507+{ 1508+ struct lpi2c_imx_struct *lpi2c_imx; 1509+ 1510+ lpi2c_imx = container_of(adap, struct lpi2c_imx_struct, adapter); 1511+ 1512+ pinctrl_select_state(lpi2c_imx->pinctrl, lpi2c_imx->pinctrl_pins_gpio); 1513+} 1514+ 1515+static void lpi2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1516+{ 1517+ struct lpi2c_imx_struct *lpi2c_imx; 1518+ 1519+ lpi2c_imx = container_of(adap, struct lpi2c_imx_struct, adapter); 1520+ 1521+ pinctrl_select_state(lpi2c_imx->pinctrl, lpi2c_imx->pinctrl_pins_default); 1522+} 1523+ 1524+/* 1525+ * We switch SCL and SDA to their GPIO function and do some bitbanging 1526+ * for bus recovery. These alternative pinmux settings can be 1527+ * described in the device tree by a separate pinctrl state "gpio". If 1528+ * this is missing this is not a big problem, the only implication is 1529+ * that we can't do bus recovery. 1530+ */ 1531+static int lpi2c_imx_init_recovery_info(struct lpi2c_imx_struct *lpi2c_imx, 1532+ struct platform_device *pdev) 1533+{ 1534+ struct i2c_bus_recovery_info *rinfo = &lpi2c_imx->rinfo; 1535+ 1536+ lpi2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1537+ if (!lpi2c_imx->pinctrl || IS_ERR(lpi2c_imx->pinctrl)) { 1538+ dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1539+ return PTR_ERR(lpi2c_imx->pinctrl); 1540+ } 1541+ 1542+ lpi2c_imx->pinctrl_pins_default = pinctrl_lookup_state(lpi2c_imx->pinctrl, 1543+ PINCTRL_STATE_DEFAULT); 1544+ lpi2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(lpi2c_imx->pinctrl, 1545+ "gpio"); 1546+ rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1547+ rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1548+ 1549+ if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1550+ PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1551+ return -EPROBE_DEFER; 1552+ } else if (IS_ERR(rinfo->sda_gpiod) || 1553+ IS_ERR(rinfo->scl_gpiod) || 1554+ IS_ERR(lpi2c_imx->pinctrl_pins_default) || 1555+ IS_ERR(lpi2c_imx->pinctrl_pins_gpio)) { 1556+ dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1557+ return 0; 1558+ } 1559+ 1560+ dev_info(&pdev->dev, "using scl%s for recovery\n", 1561+ rinfo->sda_gpiod ? ",sda" : ""); 1562+ 1563+ rinfo->prepare_recovery = lpi2c_imx_prepare_recovery; 1564+ rinfo->unprepare_recovery = lpi2c_imx_unprepare_recovery; 1565+ rinfo->recover_bus = i2c_generic_scl_recovery; 1566+ lpi2c_imx->adapter.bus_recovery_info = rinfo; 1567+ 1568+ return 0; 1569+} 1570+ 1571 static u32 lpi2c_imx_func(struct i2c_adapter *adapter) 1572 { 1573 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1574@@ -536,23 +824,97 @@ static const struct of_device_id lpi2c_imx_of_match[] = { 1575 }; 1576 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); 1577 1578+static void lpi2c_dma_exit(struct lpi2c_imx_struct *lpi2c_imx) 1579+{ 1580+ if (lpi2c_imx->dma_rx) { 1581+ dma_release_channel(lpi2c_imx->dma_rx); 1582+ lpi2c_imx->dma_rx = NULL; 1583+ } 1584+ 1585+ if (lpi2c_imx->dma_tx) { 1586+ dma_release_channel(lpi2c_imx->dma_tx); 1587+ lpi2c_imx->dma_tx = NULL; 1588+ } 1589+} 1590+ 1591+static int lpi2c_dma_init(struct device *dev, 1592+ struct lpi2c_imx_struct *lpi2c_imx) 1593+{ 1594+ int ret; 1595+ struct dma_slave_config dma_sconfig; 1596+ 1597+ /* Prepare for TX DMA: */ 1598+ lpi2c_imx->dma_tx = dma_request_chan(dev, "tx"); 1599+ if (IS_ERR(lpi2c_imx->dma_tx)) { 1600+ ret = PTR_ERR(lpi2c_imx->dma_tx); 1601+ dev_err(dev, "can't get the TX DMA channel, error %d!\n", ret); 1602+ lpi2c_imx->dma_tx = NULL; 1603+ goto err; 1604+ } 1605+ 1606+ dma_sconfig.dst_addr = lpi2c_imx->phy_addr + LPI2C_MTDR; 1607+ dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1608+ dma_sconfig.dst_maxburst = 1; 1609+ dma_sconfig.direction = DMA_MEM_TO_DEV; 1610+ ret = dmaengine_slave_config(lpi2c_imx->dma_tx, &dma_sconfig); 1611+ if (ret < 0) { 1612+ dev_err(dev, "can't configure tx channel (%d)\n", ret); 1613+ goto fail_tx; 1614+ } 1615+ 1616+ /* Prepare for RX DMA: */ 1617+ lpi2c_imx->dma_rx = dma_request_chan(dev, "rx"); 1618+ if (IS_ERR(lpi2c_imx->dma_rx)) { 1619+ ret = PTR_ERR(lpi2c_imx->dma_rx); 1620+ dev_err(dev, "can't get the RX DMA channel, error %d\n", ret); 1621+ lpi2c_imx->dma_rx = NULL; 1622+ goto fail_tx; 1623+ } 1624+ 1625+ dma_sconfig.src_addr = lpi2c_imx->phy_addr + LPI2C_MRDR; 1626+ dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1627+ dma_sconfig.src_maxburst = 1; 1628+ dma_sconfig.direction = DMA_DEV_TO_MEM; 1629+ ret = dmaengine_slave_config(lpi2c_imx->dma_rx, &dma_sconfig); 1630+ if (ret < 0) { 1631+ dev_err(dev, "can't configure rx channel (%d)\n", ret); 1632+ goto fail_rx; 1633+ } 1634+ 1635+ lpi2c_imx->can_use_dma = true; 1636+ lpi2c_imx->using_dma = false; 1637+ 1638+ return 0; 1639+fail_rx: 1640+ dma_release_channel(lpi2c_imx->dma_rx); 1641+fail_tx: 1642+ dma_release_channel(lpi2c_imx->dma_tx); 1643+err: 1644+ lpi2c_dma_exit(lpi2c_imx); 1645+ lpi2c_imx->can_use_dma = false; 1646+ return ret; 1647+} 1648+ 1649 static int lpi2c_imx_probe(struct platform_device *pdev) 1650 { 1651 struct lpi2c_imx_struct *lpi2c_imx; 1652 unsigned int temp; 1653- int irq, ret; 1654+ int ret; 1655+ struct resource *res; 1656 1657 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL); 1658 if (!lpi2c_imx) 1659 return -ENOMEM; 1660 1661+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1662 lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0); 1663 if (IS_ERR(lpi2c_imx->base)) 1664 return PTR_ERR(lpi2c_imx->base); 1665 1666- irq = platform_get_irq(pdev, 0); 1667- if (irq < 0) 1668- return irq; 1669+ lpi2c_imx->phy_addr = (dma_addr_t)res->start; 1670+ lpi2c_imx->irq = platform_get_irq(pdev, 0); 1671+ if (lpi2c_imx->irq < 0) 1672+ return lpi2c_imx->irq; 1673 1674 lpi2c_imx->adapter.owner = THIS_MODULE; 1675 lpi2c_imx->adapter.algo = &lpi2c_imx_algo; 1676@@ -561,10 +923,16 @@ static int lpi2c_imx_probe(struct platform_device *pdev) 1677 strlcpy(lpi2c_imx->adapter.name, pdev->name, 1678 sizeof(lpi2c_imx->adapter.name)); 1679 1680- lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1681- if (IS_ERR(lpi2c_imx->clk)) { 1682+ lpi2c_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1683+ if (IS_ERR(lpi2c_imx->clk_per)) { 1684 dev_err(&pdev->dev, "can't get I2C peripheral clock\n"); 1685- return PTR_ERR(lpi2c_imx->clk); 1686+ return PTR_ERR(lpi2c_imx->clk_per); 1687+ } 1688+ 1689+ lpi2c_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1690+ if (IS_ERR(lpi2c_imx->clk_ipg)) { 1691+ dev_err(&pdev->dev, "can't get I2C ipg clock\n"); 1692+ return PTR_ERR(lpi2c_imx->clk_ipg); 1693 } 1694 1695 ret = of_property_read_u32(pdev->dev.of_node, 1696@@ -572,32 +940,36 @@ static int lpi2c_imx_probe(struct platform_device *pdev) 1697 if (ret) 1698 lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1699 1700- ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0, 1701- pdev->name, lpi2c_imx); 1702- if (ret) { 1703- dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1704- return ret; 1705- } 1706- 1707 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx); 1708 platform_set_drvdata(pdev, lpi2c_imx); 1709 1710- ret = clk_prepare_enable(lpi2c_imx->clk); 1711- if (ret) { 1712- dev_err(&pdev->dev, "clk enable failed %d\n", ret); 1713- return ret; 1714- } 1715- 1716 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1717 pm_runtime_use_autosuspend(&pdev->dev); 1718- pm_runtime_get_noresume(&pdev->dev); 1719- pm_runtime_set_active(&pdev->dev); 1720 pm_runtime_enable(&pdev->dev); 1721 1722+ pm_runtime_get_sync(&pdev->dev); 1723 temp = readl(lpi2c_imx->base + LPI2C_PARAM); 1724 lpi2c_imx->txfifosize = 1 << (temp & 0x0f); 1725 lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f); 1726 1727+ /* Init optional bus recovery function */ 1728+ ret = lpi2c_imx_init_recovery_info(lpi2c_imx, pdev); 1729+ /* Give it another chance if pinctrl used is not ready yet */ 1730+ if (ret == -EPROBE_DEFER) 1731+ goto rpm_disable; 1732+ 1733+ /* Init DMA */ 1734+ lpi2c_imx->dma_direction = DMA_NONE; 1735+ lpi2c_imx->dma_rx = lpi2c_imx->dma_tx = NULL; 1736+ ret = lpi2c_dma_init(&pdev->dev, lpi2c_imx); 1737+ if (ret) { 1738+ dev_err_probe(&pdev->dev, ret, "dma setup error %d, use pio\n", ret); 1739+ if (ret == -EPROBE_DEFER) 1740+ goto rpm_disable; 1741+ } 1742+ 1743+ init_completion(&lpi2c_imx->complete); 1744+ 1745 ret = i2c_add_adapter(&lpi2c_imx->adapter); 1746 if (ret) 1747 goto rpm_disable; 1748@@ -610,9 +982,9 @@ static int lpi2c_imx_probe(struct platform_device *pdev) 1749 return 0; 1750 1751 rpm_disable: 1752- pm_runtime_put(&pdev->dev); 1753- pm_runtime_disable(&pdev->dev); 1754 pm_runtime_dont_use_autosuspend(&pdev->dev); 1755+ pm_runtime_put_sync(&pdev->dev); 1756+ pm_runtime_disable(&pdev->dev); 1757 1758 return ret; 1759 } 1760@@ -633,8 +1005,10 @@ static int __maybe_unused lpi2c_runtime_suspend(struct device *dev) 1761 { 1762 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 1763 1764- clk_disable_unprepare(lpi2c_imx->clk); 1765- pinctrl_pm_select_sleep_state(dev); 1766+ devm_free_irq(dev, lpi2c_imx->irq, lpi2c_imx); 1767+ clk_disable_unprepare(lpi2c_imx->clk_ipg); 1768+ clk_disable_unprepare(lpi2c_imx->clk_per); 1769+ pinctrl_pm_select_idle_state(dev); 1770 1771 return 0; 1772 } 1773@@ -645,18 +1019,50 @@ static int __maybe_unused lpi2c_runtime_resume(struct device *dev) 1774 int ret; 1775 1776 pinctrl_pm_select_default_state(dev); 1777- ret = clk_prepare_enable(lpi2c_imx->clk); 1778+ ret = clk_prepare_enable(lpi2c_imx->clk_per); 1779 if (ret) { 1780- dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret); 1781+ dev_err(dev, "can't enable I2C per clock, ret=%d\n", ret); 1782 return ret; 1783 } 1784 1785+ ret = clk_prepare_enable(lpi2c_imx->clk_ipg); 1786+ if (ret) { 1787+ clk_disable_unprepare(lpi2c_imx->clk_per); 1788+ dev_err(dev, "can't enable I2C ipg clock, ret=%d\n", ret); 1789+ } 1790+ 1791+ ret = devm_request_irq(dev, lpi2c_imx->irq, lpi2c_imx_isr, 1792+ IRQF_NO_SUSPEND, 1793+ dev_name(dev), lpi2c_imx); 1794+ if (ret) { 1795+ dev_err(dev, "can't claim irq %d\n", lpi2c_imx->irq); 1796+ return ret; 1797+ } 1798+ 1799+ return ret; 1800+} 1801+ 1802+static int lpi2c_suspend_noirq(struct device *dev) 1803+{ 1804+ int ret; 1805+ 1806+ ret = pm_runtime_force_suspend(dev); 1807+ if (ret) 1808+ return ret; 1809+ 1810+ pinctrl_pm_select_sleep_state(dev); 1811+ 1812 return 0; 1813 } 1814 1815+static int lpi2c_resume_noirq(struct device *dev) 1816+{ 1817+ return pm_runtime_force_resume(dev); 1818+} 1819+ 1820 static const struct dev_pm_ops lpi2c_pm_ops = { 1821- SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1822- pm_runtime_force_resume) 1823+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(lpi2c_suspend_noirq, 1824+ lpi2c_resume_noirq) 1825 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, 1826 lpi2c_runtime_resume, NULL) 1827 }; 1828@@ -671,7 +1077,17 @@ static struct platform_driver lpi2c_imx_driver = { 1829 }, 1830 }; 1831 1832-module_platform_driver(lpi2c_imx_driver); 1833+static int __init lpi2c_imx_init(void) 1834+{ 1835+ return platform_driver_register(&lpi2c_imx_driver); 1836+} 1837+subsys_initcall(lpi2c_imx_init); 1838+ 1839+static void __exit lpi2c_imx_exit(void) 1840+{ 1841+ platform_driver_unregister(&lpi2c_imx_driver); 1842+} 1843+module_exit(lpi2c_imx_exit); 1844 1845 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 1846 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus"); 1847diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c 1848index 72af4b4d1..b0764f7ab 100644 1849--- a/drivers/i2c/busses/i2c-imx.c 1850+++ b/drivers/i2c/busses/i2c-imx.c 1851@@ -40,16 +40,24 @@ 1852 #include <linux/of.h> 1853 #include <linux/of_device.h> 1854 #include <linux/of_dma.h> 1855+#include <linux/of_gpio.h> 1856 #include <linux/pinctrl/consumer.h> 1857 #include <linux/platform_data/i2c-imx.h> 1858 #include <linux/platform_device.h> 1859 #include <linux/pm_runtime.h> 1860 #include <linux/sched.h> 1861 #include <linux/slab.h> 1862+#include <linux/gpio.h> 1863+#include <linux/of_address.h> 1864+#include <linux/of.h> 1865+#include <linux/of_device.h> 1866+#include <linux/libata.h> 1867 1868 /* This will be the driver name the kernel reports */ 1869 #define DRIVER_NAME "imx-i2c" 1870 1871+#define IMX_I2C_MAX_E_BIT_RATE 384000 /* 384kHz from e7805 errata*/ 1872+ 1873 /* 1874 * Enable DMA if transfer byte size is bigger than this threshold. 1875 * As the hardware request, it must bigger than 4 bytes.\ 1876@@ -105,7 +113,56 @@ 1877 #define I2CR_IEN_OPCODE_0 0x0 1878 #define I2CR_IEN_OPCODE_1 I2CR_IEN 1879 1880-#define I2C_PM_TIMEOUT 10 /* ms */ 1881+#define I2C_PM_TIMEOUT 1000 /* ms */ 1882+ 1883+enum pinmux_endian_type { 1884+ BIG_ENDIAN, 1885+ LITTLE_ENDIAN, 1886+}; 1887+ 1888+struct pinmux_cfg { 1889+ enum pinmux_endian_type endian; /* endian of RCWPMUXCR0 */ 1890+ u32 pmuxcr_offset; 1891+ u32 pmuxcr_set_bit; /* pin mux of RCWPMUXCR0 */ 1892+}; 1893+ 1894+static struct pinmux_cfg ls1012a_pinmux_cfg = { 1895+ .endian = BIG_ENDIAN, 1896+ .pmuxcr_offset = 0x430, 1897+ .pmuxcr_set_bit = 0x10, 1898+}; 1899+ 1900+static struct pinmux_cfg ls1043a_pinmux_cfg = { 1901+ .endian = BIG_ENDIAN, 1902+ .pmuxcr_offset = 0x40C, 1903+ .pmuxcr_set_bit = 0x10, 1904+}; 1905+ 1906+static struct pinmux_cfg ls1046a_pinmux_cfg = { 1907+ .endian = BIG_ENDIAN, 1908+ .pmuxcr_offset = 0x40C, 1909+ .pmuxcr_set_bit = 0x80000000, 1910+}; 1911+ 1912+static const struct of_device_id pinmux_of_match[] = { 1913+ { .compatible = "fsl,ls1012a-vf610-i2c", .data = &ls1012a_pinmux_cfg}, 1914+ { .compatible = "fsl,ls1043a-vf610-i2c", .data = &ls1043a_pinmux_cfg}, 1915+ { .compatible = "fsl,ls1046a-vf610-i2c", .data = &ls1046a_pinmux_cfg}, 1916+ {}, 1917+}; 1918+MODULE_DEVICE_TABLE(of, pinmux_of_match); 1919+ 1920+/* The SCFG, Supplemental Configuration Unit, provides SoC specific 1921+ * configuration and status registers for the device. There is a 1922+ * SDHC IO VSEL control register on SCFG for some platforms. It's 1923+ * used to support SDHC IO voltage switching. 1924+ */ 1925+static const struct of_device_id scfg_device_ids[] = { 1926+ { .compatible = "fsl,ls1012a-scfg", }, 1927+ { .compatible = "fsl,ls1043a-scfg", }, 1928+ { .compatible = "fsl,ls1046a-scfg", }, 1929+ {} 1930+}; 1931 1932 /* 1933 * sorted list of clock divider, register value pairs 1934@@ -159,6 +216,7 @@ enum imx_i2c_type { 1935 IMX1_I2C, 1936 IMX21_I2C, 1937 VF610_I2C, 1938+ IMX7D_I2C, 1939 }; 1940 1941 struct imx_i2c_hwdata { 1942@@ -201,6 +259,15 @@ struct imx_i2c_struct { 1943 struct pinctrl_state *pinctrl_pins_gpio; 1944 1945 struct imx_i2c_dma *dma; 1946+ int layerscape_bus_recover; 1947+ int gpio; 1948+ int need_set_pmuxcr; 1949+ int pmuxcr_set; 1950+ int pmuxcr_endian; 1951+ void __iomem *pmuxcr_addr; 1952+#if IS_ENABLED(CONFIG_I2C_SLAVE) 1953+ struct i2c_client *slave; 1954+#endif 1955 }; 1956 1957 static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 1958@@ -233,6 +300,16 @@ static struct imx_i2c_hwdata vf610_i2c_hwdata = { 1959 1960 }; 1961 1962+static const struct imx_i2c_hwdata imx7d_i2c_hwdata = { 1963+ .devtype = IMX7D_I2C, 1964+ .regshift = IMX_I2C_REGSHIFT, 1965+ .clk_div = imx_i2c_clk_div, 1966+ .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 1967+ .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 1968+ .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 1969+ 1970+}; 1971+ 1972 static const struct platform_device_id imx_i2c_devtype[] = { 1973 { 1974 .name = "imx1-i2c", 1975@@ -250,6 +327,7 @@ static const struct of_device_id i2c_imx_dt_ids[] = { 1976 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 1977 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 1978 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 1979+ { .compatible = "fsl,imx7d-i2c", .data = &imx7d_i2c_hwdata, }, 1980 { /* sentinel */ } 1981 }; 1982 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 1983@@ -260,11 +338,20 @@ static const struct acpi_device_id i2c_imx_acpi_ids[] = { 1984 }; 1985 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 1986 1987+#if IS_ENABLED(CONFIG_I2C_SLAVE) 1988+static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx); 1989+#endif 1990+ 1991 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 1992 { 1993 return i2c_imx->hwdata->devtype == IMX1_I2C; 1994 } 1995 1996+static inline int is_imx7d_i2c(struct imx_i2c_struct *i2c_imx) 1997+{ 1998+ return i2c_imx->hwdata->devtype == IMX7D_I2C; 1999+} 2000+ 2001 static inline void imx_i2c_write_reg(unsigned int val, 2002 struct imx_i2c_struct *i2c_imx, unsigned int reg) 2003 { 2004@@ -277,9 +364,17 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 2005 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 2006 } 2007 2008+/* Set up i2c controller register and i2c status register to default value. */ 2009+static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx) 2010+{ 2011+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 2012+ i2c_imx, IMX_I2C_I2CR); 2013+ imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 2014+} 2015+ 2016 /* Functions for DMA support */ 2017-static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 2018- dma_addr_t phy_addr) 2019+static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 2020+ dma_addr_t phy_addr) 2021 { 2022 struct imx_i2c_dma *dma; 2023 struct dma_slave_config dma_sconfig; 2024@@ -288,7 +383,7 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 2025 2026 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 2027 if (!dma) 2028- return; 2029+ return -ENOMEM; 2030 2031 dma->chan_tx = dma_request_chan(dev, "tx"); 2032 if (IS_ERR(dma->chan_tx)) { 2033@@ -333,7 +428,7 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 2034 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 2035 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 2036 2037- return; 2038+ return 0; 2039 2040 fail_rx: 2041 dma_release_channel(dma->chan_rx); 2042@@ -341,6 +436,8 @@ static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 2043 dma_release_channel(dma->chan_tx); 2044 fail_al: 2045 devm_kfree(dev, dma); 2046+ 2047+ return ret; 2048 } 2049 2050 static void i2c_imx_dma_callback(void *arg) 2051@@ -425,6 +522,14 @@ static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 2052 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 2053 } 2054 2055+/* Clear arbitration lost bit */ 2056+static void i2c_imx_clr_al_bit(unsigned int status, struct imx_i2c_struct *i2c_imx) 2057+{ 2058+ status &= ~I2SR_IAL; 2059+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL); 2060+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); 2061+} 2062+ 2063 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 2064 { 2065 unsigned long orig_jiffies = jiffies; 2066@@ -437,7 +542,7 @@ static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool a 2067 2068 /* check for arbitration lost */ 2069 if (temp & I2SR_IAL) { 2070- i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 2071+ i2c_imx_clr_al_bit(temp, i2c_imx); 2072 return -EAGAIN; 2073 } 2074 2075@@ -491,15 +596,6 @@ static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 2076 return -ETIMEDOUT; 2077 } 2078 2079- /* check for arbitration lost */ 2080- if (i2c_imx->i2csr & I2SR_IAL) { 2081- dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 2082- i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 2083- 2084- i2c_imx->i2csr = 0; 2085- return -EAGAIN; 2086- } 2087- 2088 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 2089 i2c_imx->i2csr = 0; 2090 return 0; 2091@@ -516,16 +612,24 @@ static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 2092 return 0; 2093 } 2094 2095-static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 2096+static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 2097 unsigned int i2c_clk_rate) 2098 { 2099 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 2100 unsigned int div; 2101 int i; 2102 2103- /* Divider value calculation */ 2104 if (i2c_imx->cur_clk == i2c_clk_rate) 2105- return; 2106+ return 0; 2107+ 2108+ /* 2109+ * Keep the denominator of the following program 2110+ * always NOT equal to 0. 2111+ */ 2112+ 2113+ /* Divider value calculation */ 2114+ if (!(i2c_clk_rate / 2)) 2115+ return -EINVAL; 2116 2117 i2c_imx->cur_clk = i2c_clk_rate; 2118 2119@@ -556,20 +660,23 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 2120 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 2121 i2c_clk_div[i].val, i2c_clk_div[i].div); 2122 #endif 2123+ 2124+ return 0; 2125 } 2126 2127 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 2128 unsigned long action, void *data) 2129 { 2130+ int ret = 0; 2131 struct clk_notifier_data *ndata = data; 2132 struct imx_i2c_struct *i2c_imx = container_of(nb, 2133 struct imx_i2c_struct, 2134 clk_change_nb); 2135 2136 if (action & POST_RATE_CHANGE) 2137- i2c_imx_set_clk(i2c_imx, ndata->new_rate); 2138+ ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate); 2139 2140- return NOTIFY_OK; 2141+ return notifier_from_errno(ret); 2142 } 2143 2144 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 2145@@ -579,6 +686,10 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 2146 2147 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 2148 2149+ result = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 2150+ if (result) 2151+ return result; 2152+ 2153 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 2154 /* Enable I2C controller */ 2155 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 2156@@ -604,6 +715,7 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 2157 2158 temp &= ~I2CR_DMAEN; 2159 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 2160+ 2161 return result; 2162 } 2163 2164@@ -638,21 +750,22 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 2165 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 2166 } 2167 2168-static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 2169+/* Clear interrupt flag bit */ 2170+static void i2c_imx_clr_if_bit(unsigned int status, struct imx_i2c_struct *i2c_imx) 2171 { 2172- struct imx_i2c_struct *i2c_imx = dev_id; 2173- unsigned int temp; 2174+ status &= ~I2SR_IIF; 2175+ status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF); 2176+ imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); 2177+} 2178 2179- temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 2180- if (temp & I2SR_IIF) { 2181- /* save status register */ 2182- i2c_imx->i2csr = temp; 2183- i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 2184- wake_up(&i2c_imx->queue); 2185- return IRQ_HANDLED; 2186- } 2187+static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status) 2188+{ 2189+ /* Save status register */ 2190+ i2c_imx->i2csr = status | I2SR_IIF; 2191 2192- return IRQ_NONE; 2193+ wake_up(&i2c_imx->queue); 2194+ 2195+ return IRQ_HANDLED; 2196 } 2197 2198 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 2199@@ -1027,24 +1140,133 @@ static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 2200 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 2201 (result < 0) ? "error" : "success msg", 2202 (result < 0) ? result : num); 2203+#if IS_ENABLED(CONFIG_I2C_SLAVE) 2204+ /* After data is transfered, switch to slave mode(as a receiver) */ 2205+ if (i2c_imx->slave) { 2206+ if (i2c_imx_slave_init(i2c_imx) < 0) 2207+ dev_err(&i2c_imx->adapter.dev, "failed to switch to slave mode"); 2208+ } 2209+#endif 2210+ 2211 return (result < 0) ? result : num; 2212 } 2213 2214+/* 2215+ * Based on the I2C specification, if the data line (SDA) is 2216+ * stuck low, the master should send nine * clock pulses. 2217+ * The I2C slave device that held the bus low should release it 2218+ * sometime within * those nine clocks. Due to this erratum, 2219+ * the I2C controller cannot generate nine clock pulses. 2220+ */ 2221+static int i2c_imx_recovery_for_layerscape(struct imx_i2c_struct *i2c_imx) 2222+{ 2223+ u32 pmuxcr = 0; 2224+ int ret; 2225+ unsigned int i, temp; 2226+ 2227+ /* configure IICx_SCL/GPIO pin as a GPIO */ 2228+ if (i2c_imx->need_set_pmuxcr == 1) { 2229+ pmuxcr = ioread32be(i2c_imx->pmuxcr_addr); 2230+ if (i2c_imx->pmuxcr_endian == BIG_ENDIAN) 2231+ iowrite32be(i2c_imx->pmuxcr_set|pmuxcr, 2232+ i2c_imx->pmuxcr_addr); 2233+ else 2234+ iowrite32(i2c_imx->pmuxcr_set|pmuxcr, 2235+ i2c_imx->pmuxcr_addr); 2236+ } 2237+ 2238+ ret = gpio_request(i2c_imx->gpio, i2c_imx->adapter.name); 2239+ if (ret) { 2240+ dev_err(&i2c_imx->adapter.dev, 2241+ "can't get gpio: %d\n", ret); 2242+ return ret; 2243+ } 2244+ 2245+ /* Configure GPIO pin as an output and open drain. */ 2246+ gpio_direction_output(i2c_imx->gpio, 1); 2247+ udelay(10); 2248+ 2249+ /* Write data to generate 9 pulses */ 2250+ for (i = 0; i < 9; i++) { 2251+ gpio_set_value(i2c_imx->gpio, 1); 2252+ udelay(10); 2253+ gpio_set_value(i2c_imx->gpio, 0); 2254+ udelay(10); 2255+ } 2256+ /* ensure that the last level sent is always high */ 2257+ gpio_set_value(i2c_imx->gpio, 1); 2258+ 2259+ /* 2260+ * Set I2Cx_IBCR = 0h00 to generate a STOP 2261+ */ 2262+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 2263+ 2264+ /* 2265+ * Set I2Cx_IBCR = 0h80 to reset the I2Cx controller 2266+ */ 2267+ imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode | I2CR_IEN, i2c_imx, IMX_I2C_I2CR); 2268+ 2269+ /* Restore the saved value of the register SCFG_RCWPMUXCR0 */ 2270+ if (i2c_imx->need_set_pmuxcr == 1) { 2271+ if (i2c_imx->pmuxcr_endian == BIG_ENDIAN) 2272+ iowrite32be(pmuxcr, i2c_imx->pmuxcr_addr); 2273+ else 2274+ iowrite32(pmuxcr, i2c_imx->pmuxcr_addr); 2275+ } 2276+ /* 2277+ * Set I2C_IBSR[IBAL] to clear the IBAL bit if- 2278+ * I2C_IBSR[IBAL] = 1 2279+ */ 2280+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 2281+ if (temp & I2SR_IAL) 2282+ i2c_imx_clr_al_bit(temp, i2c_imx); 2283+ 2284+ return 0; 2285+} 2286+ 2287 static int i2c_imx_xfer(struct i2c_adapter *adapter, 2288 struct i2c_msg *msgs, int num) 2289 { 2290 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 2291+ bool enable_runtime_pm = false; 2292 int result; 2293 2294+ if (!pm_runtime_enabled(i2c_imx->adapter.dev.parent)) { 2295+ pm_runtime_enable(i2c_imx->adapter.dev.parent); 2296+ enable_runtime_pm = true; 2297+ } 2298+ 2299 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 2300- if (result < 0) 2301+ if (result < 0) { 2302+ if (enable_runtime_pm) 2303+ pm_runtime_disable(i2c_imx->adapter.dev.parent); 2304 return result; 2305+ } 2306+ 2307+ /* 2308+ * workaround for ERR010027: ensure that the I2C BUS is idle 2309+ * before switching to master mode and attempting a Start cycle 2310+ */ 2311+ result = i2c_imx_bus_busy(i2c_imx, 0, false); 2312+ if (result) { 2313+ /* timeout */ 2314+ if ((result == -ETIMEDOUT) && (i2c_imx->layerscape_bus_recover == 1)) 2315+ i2c_imx_recovery_for_layerscape(i2c_imx); 2316+ else { 2317+ if (enable_runtime_pm) 2318+ pm_runtime_disable(i2c_imx->adapter.dev.parent); 2319+ return result; 2320+ } 2321+ } 2322 2323 result = i2c_imx_xfer_common(adapter, msgs, num, false); 2324 2325 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 2326 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 2327 2328+ if (enable_runtime_pm) 2329+ pm_runtime_disable(i2c_imx->adapter.dev.parent); 2330+ 2331 return result; 2332 } 2333 2334@@ -1130,18 +1352,213 @@ static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 2335 return 0; 2336 } 2337 2338+/* 2339+ * switch SCL and SDA to their GPIO function and do some bitbanging 2340+ * for bus recovery. 2341+ * There are platforms such as Layerscape that don't support pinctrl, so add 2342+ * workaround for layerscape, it has no effect for other platforms. 2343+ */ 2344+static int i2c_imx_init_recovery_for_layerscape( 2345+ struct imx_i2c_struct *i2c_imx, 2346+ struct platform_device *pdev) 2347+{ 2348+ const struct of_device_id *of_id; 2349+ struct device_node *np = pdev->dev.of_node; 2350+ struct pinmux_cfg *pinmux_cfg; 2351+ struct device_node *scfg_node; 2352+ void __iomem *scfg_base = NULL; 2353+ 2354+ i2c_imx->gpio = of_get_named_gpio(np, "scl-gpios", 0); 2355+ if (!gpio_is_valid(i2c_imx->gpio)) { 2356+ dev_info(&pdev->dev, "scl-gpios not found\n"); 2357+ return 0; 2358+ } 2359+ pinmux_cfg = devm_kzalloc(&pdev->dev, sizeof(*pinmux_cfg), GFP_KERNEL); 2360+ if (!pinmux_cfg) 2361+ return -ENOMEM; 2362+ 2363+ i2c_imx->need_set_pmuxcr = 0; 2364+ of_id = of_match_node(pinmux_of_match, np); 2365+ if (of_id) { 2366+ pinmux_cfg = (struct pinmux_cfg *)of_id->data; 2367+ i2c_imx->pmuxcr_endian = pinmux_cfg->endian; 2368+ i2c_imx->pmuxcr_set = pinmux_cfg->pmuxcr_set_bit; 2369+ scfg_node = of_find_matching_node(NULL, scfg_device_ids); 2370+ if (scfg_node) { 2371+ scfg_base = of_iomap(scfg_node, 0); 2372+ if (scfg_base) { 2373+ i2c_imx->pmuxcr_addr = scfg_base + pinmux_cfg->pmuxcr_offset; 2374+ i2c_imx->need_set_pmuxcr = 1; 2375+ } 2376+ } 2377+ } 2378+ i2c_imx->layerscape_bus_recover = 1; 2379+ return 0; 2380+} 2381+ 2382 static u32 i2c_imx_func(struct i2c_adapter *adapter) 2383 { 2384 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 2385 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 2386 } 2387 2388+#if IS_ENABLED(CONFIG_I2C_SLAVE) 2389+static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) 2390+{ 2391+ int temp; 2392+ 2393+ /* Resume */ 2394+ temp = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 2395+ if (temp < 0) { 2396+ dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller"); 2397+ return temp; 2398+ } 2399+ 2400+ /* Set slave addr. */ 2401+ imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR); 2402+ 2403+ i2c_imx_reset_regs(i2c_imx); 2404+ 2405+ /* Enable module */ 2406+ temp = i2c_imx->hwdata->i2cr_ien_opcode; 2407+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 2408+ 2409+ /* Enable interrupt from i2c module */ 2410+ temp |= I2CR_IIEN; 2411+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 2412+ 2413+ /* Wait controller to be stable */ 2414+ usleep_range(50, 150); 2415+ return 0; 2416+} 2417+ 2418+static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx, unsigned int status, unsigned int ctl) 2419+{ 2420+ u8 value; 2421+ 2422+ if (status & I2SR_IAL) { /* Arbitration lost */ 2423+ i2c_imx_clr_al_bit(status | I2SR_IIF, i2c_imx); 2424+ } else if (status & I2SR_IAAS) { /* Addressed as a slave */ 2425+ if (status & I2SR_SRW) { /* Master wants to read from us*/ 2426+ dev_dbg(&i2c_imx->adapter.dev, "read requested"); 2427+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value); 2428+ 2429+ /* Slave transmit */ 2430+ ctl |= I2CR_MTX; 2431+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 2432+ 2433+ /* Send data */ 2434+ imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 2435+ } else { /* Master wants to write to us */ 2436+ dev_dbg(&i2c_imx->adapter.dev, "write requested"); 2437+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value); 2438+ 2439+ /* Slave receive */ 2440+ ctl &= ~I2CR_MTX; 2441+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 2442+ /* Dummy read */ 2443+ imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 2444+ } 2445+ } else if (!(ctl & I2CR_MTX)) { /* Receive mode */ 2446+ if (status & I2SR_IBB) { /* No STOP signal detected */ 2447+ ctl &= ~I2CR_MTX; 2448+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 2449+ 2450+ value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 2451+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value); 2452+ } else { /* STOP signal is detected */ 2453+ dev_dbg(&i2c_imx->adapter.dev, 2454+ "STOP signal detected"); 2455+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value); 2456+ } 2457+ } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */ 2458+ ctl |= I2CR_MTX; 2459+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 2460+ 2461+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value); 2462+ 2463+ imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR); 2464+ } else { /* Transmit mode received NAK */ 2465+ ctl &= ~I2CR_MTX; 2466+ imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR); 2467+ imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 2468+ i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value); 2469+ } 2470+ 2471+ return IRQ_HANDLED; 2472+} 2473+ 2474+static int i2c_imx_reg_slave(struct i2c_client *client) 2475+{ 2476+ struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 2477+ int ret; 2478+ if (i2c_imx->slave) 2479+ return -EBUSY; 2480+ 2481+ i2c_imx->slave = client; 2482+ 2483+ ret = i2c_imx_slave_init(i2c_imx); 2484+ if (ret < 0) 2485+ dev_err(&i2c_imx->adapter.dev, "failed to switch to slave mode"); 2486+ 2487+ return ret; 2488+} 2489+ 2490+static int i2c_imx_unreg_slave(struct i2c_client *client) 2491+{ 2492+ struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter); 2493+ int ret; 2494+ 2495+ if (!i2c_imx->slave) 2496+ return -EINVAL; 2497+ 2498+ /* Reset slave address. */ 2499+ imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 2500+ 2501+ i2c_imx_reset_regs(i2c_imx); 2502+ 2503+ i2c_imx->slave = NULL; 2504+ 2505+ /* Suspend */ 2506+ ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent); 2507+ if (ret < 0) 2508+ dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller"); 2509+ 2510+ return ret; 2511+} 2512+#endif 2513+ 2514 static const struct i2c_algorithm i2c_imx_algo = { 2515 .master_xfer = i2c_imx_xfer, 2516 .master_xfer_atomic = i2c_imx_xfer_atomic, 2517 .functionality = i2c_imx_func, 2518+#if IS_ENABLED(CONFIG_I2C_SLAVE) 2519+ .reg_slave = i2c_imx_reg_slave, 2520+ .unreg_slave = i2c_imx_unreg_slave, 2521+#endif 2522 }; 2523 2524+static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 2525+{ 2526+ struct imx_i2c_struct *i2c_imx = dev_id; 2527+ unsigned int ctl, status; 2528+ 2529+ status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 2530+ ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 2531+ 2532+ if (status & I2SR_IIF) { 2533+ i2c_imx_clr_if_bit(status, i2c_imx); 2534+#if IS_ENABLED(CONFIG_I2C_SLAVE) 2535+ if (i2c_imx->slave && !(ctl & I2CR_MSTA)) { 2536+ return i2c_imx_slave_isr(i2c_imx, status, ctl); 2537+ } 2538+#endif 2539+ return i2c_imx_master_isr(i2c_imx, status); 2540+ } 2541+ 2542+ return IRQ_NONE; 2543+} 2544+ 2545 static int i2c_imx_probe(struct platform_device *pdev) 2546 { 2547 struct imx_i2c_struct *i2c_imx; 2548@@ -1211,12 +1628,13 @@ static int i2c_imx_probe(struct platform_device *pdev) 2549 pm_runtime_set_active(&pdev->dev); 2550 pm_runtime_enable(&pdev->dev); 2551 2552- ret = pm_runtime_get_sync(&pdev->dev); 2553+ ret = pm_runtime_resume_and_get(&pdev->dev); 2554 if (ret < 0) 2555 goto rpm_disable; 2556 2557 /* Request IRQ */ 2558- ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 2559+ ret = request_threaded_irq(irq, i2c_imx_isr, NULL, 2560+ IRQF_SHARED | IRQF_NO_SUSPEND, 2561 pdev->name, i2c_imx); 2562 if (ret) { 2563 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 2564@@ -1231,15 +1649,28 @@ static int i2c_imx_probe(struct platform_device *pdev) 2565 i2c_imx->bitrate = pdata->bitrate; 2566 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 2567 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 2568- i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 2569+ ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 2570+ if (ret < 0) { 2571+ dev_err(&pdev->dev, "can't get I2C clock\n"); 2572+ goto clk_notifier_unregister; 2573+ } 2574 2575- /* Set up chip registers to defaults */ 2576- imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 2577- i2c_imx, IMX_I2C_I2CR); 2578- imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 2579+ /* 2580+ * This limit caused by an i.MX7D hardware issue(e7805 in Errata). 2581+ * If there is no limit, when the bitrate set up to 400KHz, it will 2582+ * cause the SCK low level period less than 1.3us. 2583+ */ 2584+ if (is_imx7d_i2c(i2c_imx) && i2c_imx->bitrate > IMX_I2C_MAX_E_BIT_RATE) 2585+ i2c_imx->bitrate = IMX_I2C_MAX_E_BIT_RATE; 2586+ 2587+ i2c_imx_reset_regs(i2c_imx); 2588+ 2589+ /* Init optional bus recovery */ 2590+ if (of_match_node(pinmux_of_match, pdev->dev.of_node)) 2591+ ret = i2c_imx_init_recovery_for_layerscape(i2c_imx, pdev); 2592+ else 2593+ ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 2594 2595- /* Init optional bus recovery function */ 2596- ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 2597 /* Give it another chance if pinctrl used is not ready yet */ 2598 if (ret == -EPROBE_DEFER) 2599 goto clk_notifier_unregister; 2600@@ -1259,10 +1690,14 @@ static int i2c_imx_probe(struct platform_device *pdev) 2601 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 2602 2603 /* Init DMA config if supported */ 2604- i2c_imx_dma_request(i2c_imx, phy_addr); 2605+ ret = i2c_imx_dma_request(i2c_imx, phy_addr); 2606+ if (ret == -EPROBE_DEFER) 2607+ goto i2c_adapter_remove; 2608 2609 return 0; /* Return OK */ 2610 2611+i2c_adapter_remove: 2612+ i2c_del_adapter(&i2c_imx->adapter); 2613 clk_notifier_unregister: 2614 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 2615 free_irq(irq, i2c_imx); 2616@@ -1313,7 +1748,8 @@ static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 2617 { 2618 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 2619 2620- clk_disable(i2c_imx->clk); 2621+ clk_disable_unprepare(i2c_imx->clk); 2622+ pinctrl_pm_select_sleep_state(dev); 2623 2624 return 0; 2625 } 2626@@ -1323,14 +1759,28 @@ static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 2627 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 2628 int ret; 2629 2630- ret = clk_enable(i2c_imx->clk); 2631+ pinctrl_pm_select_default_state(dev); 2632+ ret = clk_prepare_enable(i2c_imx->clk); 2633 if (ret) 2634 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 2635 2636 return ret; 2637 } 2638 2639+static int i2c_imx_suspend(struct device *dev) 2640+{ 2641+ pinctrl_pm_select_sleep_state(dev); 2642+ return 0; 2643+} 2644+ 2645+static int i2c_imx_resume(struct device *dev) 2646+{ 2647+ pinctrl_pm_select_default_state(dev); 2648+ return 0; 2649+} 2650+ 2651 static const struct dev_pm_ops i2c_imx_pm_ops = { 2652+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume) 2653 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 2654 i2c_imx_runtime_resume, NULL) 2655 }; 2656diff --git a/drivers/i2c/busses/i2c-rpmsg-imx.c b/drivers/i2c/busses/i2c-rpmsg-imx.c 2657new file mode 100644 2658index 000000000..06e705271 2659--- /dev/null 2660+++ b/drivers/i2c/busses/i2c-rpmsg-imx.c 2661@@ -0,0 +1,462 @@ 2662+/* 2663+ * Copyright 2019 NXP 2664+ * 2665+ * The code contained herein is licensed under the GNU General Public 2666+ * License. You may obtain a copy of the GNU General Public License 2667+ * Version 2 or later at the following locations: 2668+ * 2669+ * http://www.opensource.org/licenses/gpl-license.html 2670+ * http://www.gnu.org/copyleft/gpl.html 2671+ */ 2672+ 2673+/* The i2c-rpmsg transfer protocol: 2674+ * 2675+ * +---------------+-------------------------------+ 2676+ * | Byte Offset | Content | 2677+ * +---------------+---+---+---+---+---+---+---+---+ 2678+ * | 0 | Category | 2679+ * +---------------+---+---+---+---+---+---+---+---+ 2680+ * | 1 ~ 2 | Version | 2681+ * +---------------+---+---+---+---+---+---+---+---+ 2682+ * | 3 | Type | 2683+ * +---------------+---+---+---+---+---+---+---+---+ 2684+ * | 4 | Command | 2685+ * +---------------+---+---+---+---+---+---+---+---+ 2686+ * | 5 | Priority | 2687+ * +---------------+---+---+---+---+---+---+---+---+ 2688+ * | 6 | Reserved1 | 2689+ * +---------------+---+---+---+---+---+---+---+---+ 2690+ * | 7 | Reserved2 | 2691+ * +---------------+---+---+---+---+---+---+---+---+ 2692+ * | 8 | Reserved3 | 2693+ * +---------------+---+---+---+---+---+---+---+---+ 2694+ * | 9 | Reserved4 | 2695+ * +---------------+---+---+---+---+---+---+---+---+ 2696+ * | 10 | BUS ID | 2697+ * +---------------+---+---+---+---+---+---+---+---+ 2698+ * | 11 | Return Value | 2699+ * +---------------+---+---+---+---+---+---+---+---+ 2700+ * | 12 ~ 13 | BUS ID | 2701+ * +---------------+---+---+---+---+---+---+---+---+ 2702+ * | 14 ~ 15 | Address | 2703+ * +---------------+---+---+---+---+---+---+---+---+ 2704+ * | 16 ~ 17 | Data Len | 2705+ * +---------------+---+---+---+---+---+---+---+---+ 2706+ * | 18 ~ 33 | 16 Bytes Data | 2707+ * +---------------+---+---+---+---+---+---+---+---+ 2708+ * 2709+ * The definition of Return Value: 2710+ * 0x00 = Success 2711+ * 0x01 = Failed 2712+ * 0x02 = Invalid parameter 2713+ * 0x03 = Invalid message 2714+ * 0x04 = Operate in invalid state 2715+ * 0x05 = Memory allocation failed 2716+ * 0x06 = Timeout when waiting for an event 2717+ * 0x07 = Cannot add to list as node already in another list 2718+ * 0x08 = Cannot remove from list as node not in list 2719+ * 0x09 = Transfer timeout 2720+ * 0x0A = Transfer failed due to peer core not ready 2721+ * 0x0B = Transfer failed due to communication failure 2722+ * 0x0C = Cannot find service for a request/notification 2723+ * 0x0D = Service version cannot support the request/notification 2724+ * 2725+ */ 2726+ 2727+#include <linux/init.h> 2728+#include <linux/io.h> 2729+#include <linux/imx_rpmsg.h> 2730+#include <linux/kernel.h> 2731+#include <linux/module.h> 2732+#include <linux/types.h> 2733+#include <linux/slab.h> 2734+#include <linux/of.h> 2735+#include <linux/of_device.h> 2736+#include <linux/i2c.h> 2737+#include <linux/platform_device.h> 2738+#include <linux/time.h> 2739+#include <linux/delay.h> 2740+#include <linux/rpmsg.h> 2741+ 2742+#define I2C_RPMSG_MAX_BUF_SIZE 16 2743+#define I2C_RPMSG_TIMEOUT 500 /* unit: ms */ 2744+ 2745+#define I2C_RPMSG_CATEGORY 0x09 2746+#define I2C_RPMSG_VERSION 0x0001 2747+#define I2C_RPMSG_TYPE_REQUEST 0x00 2748+#define I2C_RPMSG_TYPE_RESPONSE 0x01 2749+#define I2C_RPMSG_COMMAND_READ 0x00 2750+#define I2C_RPMSG_COMMAND_WRITE 0x01 2751+#define I2C_RPMSG_PRIORITY 0x01 2752+ 2753+#define I2C_RPMSG_M_STOP 0x0200 2754+ 2755+struct i2c_rpmsg_msg { 2756+ struct imx_rpmsg_head header; 2757+ 2758+ /* Payload Start*/ 2759+ u8 bus_id; 2760+ u8 ret_val; 2761+ u16 addr; 2762+ u16 flags; 2763+ u16 len; 2764+ u8 buf[I2C_RPMSG_MAX_BUF_SIZE]; 2765+} __packed __aligned(1); 2766+ 2767+struct i2c_rpmsg_info { 2768+ struct rpmsg_device *rpdev; 2769+ struct device *dev; 2770+ struct i2c_rpmsg_msg *msg; 2771+ struct completion cmd_complete; 2772+ struct mutex lock; 2773+ 2774+ u8 bus_id; 2775+ u16 addr; 2776+}; 2777+ 2778+static struct i2c_rpmsg_info i2c_rpmsg; 2779+ 2780+struct imx_rpmsg_i2c_data { 2781+ struct i2c_adapter adapter; 2782+}; 2783+ 2784+static int i2c_rpmsg_cb(struct rpmsg_device *rpdev, void *data, int len, 2785+ void *priv, u32 src) 2786+{ 2787+ struct i2c_rpmsg_msg *msg = (struct i2c_rpmsg_msg *)data; 2788+ 2789+ if (msg->header.type != I2C_RPMSG_TYPE_RESPONSE) 2790+ return -EINVAL; 2791+ 2792+ if (msg->bus_id != i2c_rpmsg.bus_id || msg->addr != i2c_rpmsg.addr) { 2793+ dev_err(&rpdev->dev, 2794+ "expected bus_id:%d, addr:%2x, received bus_id:%d, addr:%2x\n", 2795+ i2c_rpmsg.bus_id, i2c_rpmsg.addr, msg->bus_id, msg->addr); 2796+ return -EINVAL; 2797+ } 2798+ 2799+ if (msg->len > I2C_RPMSG_MAX_BUF_SIZE) { 2800+ dev_err(&rpdev->dev, 2801+ "%s failed: data length greater than %d, len=%d\n", 2802+ __func__, I2C_RPMSG_MAX_BUF_SIZE, msg->len); 2803+ return -EINVAL; 2804+ } 2805+ 2806+ /* Receive Success */ 2807+ i2c_rpmsg.msg = msg; 2808+ 2809+ complete(&i2c_rpmsg.cmd_complete); 2810+ 2811+ return 0; 2812+} 2813+ 2814+static int rpmsg_xfer(struct i2c_rpmsg_msg *rmsg, struct i2c_rpmsg_info *info) 2815+{ 2816+ int ret = 0; 2817+ 2818+ ret = rpmsg_send(info->rpdev->ept, (void *)rmsg, 2819+ sizeof(struct i2c_rpmsg_msg)); 2820+ if (ret < 0) { 2821+ dev_err(&info->rpdev->dev, "rpmsg_send failed: %d\n", ret); 2822+ return ret; 2823+ } 2824+ 2825+ ret = wait_for_completion_timeout(&info->cmd_complete, 2826+ msecs_to_jiffies(I2C_RPMSG_TIMEOUT)); 2827+ if (!ret) { 2828+ dev_err(&info->rpdev->dev, "%s failed: timeout\n", __func__); 2829+ return -ETIMEDOUT; 2830+ } 2831+ 2832+ if (info->msg->ret_val) { 2833+ dev_dbg(&info->rpdev->dev, 2834+ "%s failed: %d\n", __func__, info->msg->ret_val); 2835+ return -(info->msg->ret_val); 2836+ } 2837+ 2838+ return 0; 2839+} 2840+ 2841+static int i2c_rpmsg_read(struct i2c_msg *msg, struct i2c_rpmsg_info *info, 2842+ int bus_id, bool is_last) 2843+{ 2844+ int ret; 2845+ struct i2c_rpmsg_msg rmsg; 2846+ 2847+ if (!info->rpdev) 2848+ return -EINVAL; 2849+ 2850+ if (msg->len > I2C_RPMSG_MAX_BUF_SIZE) { 2851+ dev_err(&info->rpdev->dev, 2852+ "%s failed: data length greater than %d, len=%d\n", 2853+ __func__, I2C_RPMSG_MAX_BUF_SIZE, msg->len); 2854+ return -EINVAL; 2855+ } 2856+ 2857+ memset(&rmsg, 0, sizeof(struct i2c_rpmsg_msg)); 2858+ rmsg.header.cate = I2C_RPMSG_CATEGORY; 2859+ rmsg.header.major = I2C_RPMSG_VERSION; 2860+ rmsg.header.minor = I2C_RPMSG_VERSION >> 8; 2861+ rmsg.header.type = I2C_RPMSG_TYPE_REQUEST; 2862+ rmsg.header.cmd = I2C_RPMSG_COMMAND_READ; 2863+ rmsg.header.reserved[0] = I2C_RPMSG_PRIORITY; 2864+ rmsg.bus_id = bus_id; 2865+ rmsg.ret_val = 0; 2866+ rmsg.addr = msg->addr; 2867+ if (is_last) 2868+ rmsg.flags = msg->flags | I2C_RPMSG_M_STOP; 2869+ else 2870+ rmsg.flags = msg->flags; 2871+ rmsg.len = (msg->len); 2872+ 2873+ reinit_completion(&info->cmd_complete); 2874+ 2875+ ret = rpmsg_xfer(&rmsg, info); 2876+ if (ret) 2877+ return ret; 2878+ 2879+ if (!info->msg || 2880+ (info->msg->len != msg->len)) { 2881+ dev_err(&info->rpdev->dev, 2882+ "%s failed: %d\n", __func__, -EPROTO); 2883+ return -EPROTO; 2884+ } 2885+ 2886+ memcpy(msg->buf, info->msg->buf, info->msg->len); 2887+ 2888+ return msg->len; 2889+} 2890+ 2891+int i2c_rpmsg_write(struct i2c_msg *msg, struct i2c_rpmsg_info *info, 2892+ int bus_id, bool is_last) 2893+{ 2894+ int i, ret; 2895+ struct i2c_rpmsg_msg rmsg; 2896+ 2897+ if (!info || !info->rpdev) 2898+ return -EINVAL; 2899+ 2900+ if (msg->len > I2C_RPMSG_MAX_BUF_SIZE) { 2901+ dev_err(&info->rpdev->dev, 2902+ "%s failed: data length greater than %d, len=%d\n", 2903+ __func__, I2C_RPMSG_MAX_BUF_SIZE, msg->len); 2904+ return -EINVAL; 2905+ } 2906+ 2907+ memset(&rmsg, 0, sizeof(struct i2c_rpmsg_msg)); 2908+ rmsg.header.cate = I2C_RPMSG_CATEGORY; 2909+ rmsg.header.major = I2C_RPMSG_VERSION; 2910+ rmsg.header.minor = I2C_RPMSG_VERSION >> 8; 2911+ rmsg.header.type = I2C_RPMSG_TYPE_REQUEST; 2912+ rmsg.header.cmd = I2C_RPMSG_COMMAND_WRITE; 2913+ rmsg.header.reserved[0] = I2C_RPMSG_PRIORITY; 2914+ rmsg.bus_id = bus_id; 2915+ rmsg.ret_val = 0; 2916+ rmsg.addr = msg->addr; 2917+ if (is_last) 2918+ rmsg.flags = msg->flags | I2C_RPMSG_M_STOP; 2919+ else 2920+ rmsg.flags = msg->flags; 2921+ rmsg.len = msg->len; 2922+ 2923+ for (i = 0; i < rmsg.len; i++) 2924+ rmsg.buf[i] = msg->buf[i]; 2925+ 2926+ reinit_completion(&info->cmd_complete); 2927+ 2928+ ret = rpmsg_xfer(&rmsg, info); 2929+ if (ret) 2930+ return ret; 2931+ 2932+ return ret; 2933+} 2934+ 2935+static int i2c_rpmsg_probe(struct rpmsg_device *rpdev) 2936+{ 2937+ int ret = 0; 2938+ 2939+ if (!rpdev) { 2940+ dev_info(&rpdev->dev, "%s failed, rpdev=NULL\n", __func__); 2941+ return -EINVAL; 2942+ } 2943+ 2944+ i2c_rpmsg.rpdev = rpdev; 2945+ 2946+ mutex_init(&i2c_rpmsg.lock); 2947+ init_completion(&i2c_rpmsg.cmd_complete); 2948+ 2949+ dev_info(&rpdev->dev, "new channel: 0x%x -> 0x%x!\n", 2950+ rpdev->src, rpdev->dst); 2951+ 2952+ return ret; 2953+} 2954+ 2955+static void i2c_rpmsg_remove(struct rpmsg_device *rpdev) 2956+{ 2957+ i2c_rpmsg.rpdev = NULL; 2958+ dev_info(&rpdev->dev, "i2c rpmsg driver is removed\n"); 2959+} 2960+ 2961+static struct rpmsg_device_id i2c_rpmsg_id_table[] = { 2962+ { .name = "rpmsg-i2c-channel" }, 2963+ { }, 2964+}; 2965+ 2966+static struct rpmsg_driver i2c_rpmsg_driver = { 2967+ .drv.name = "i2c-rpmsg", 2968+ .drv.owner = THIS_MODULE, 2969+ .id_table = i2c_rpmsg_id_table, 2970+ .probe = i2c_rpmsg_probe, 2971+ .remove = i2c_rpmsg_remove, 2972+ .callback = i2c_rpmsg_cb, 2973+}; 2974+ 2975+ 2976+static int i2c_rpbus_xfer(struct i2c_adapter *adapter, 2977+ struct i2c_msg *msgs, int num) 2978+{ 2979+ struct imx_rpmsg_i2c_data *rdata = 2980+ container_of(adapter, struct imx_rpmsg_i2c_data, adapter); 2981+ struct i2c_msg *pmsg; 2982+ int i, ret; 2983+ bool is_last = false; 2984+ 2985+ mutex_lock(&i2c_rpmsg.lock); 2986+ 2987+ for (i = 0; i < num; i++) { 2988+ if (i == num - 1) 2989+ is_last = true; 2990+ 2991+ pmsg = &msgs[i]; 2992+ 2993+ i2c_rpmsg.bus_id = rdata->adapter.nr; 2994+ i2c_rpmsg.addr = pmsg->addr; 2995+ 2996+ if (pmsg->flags & I2C_M_RD) { 2997+ ret = i2c_rpmsg_read(pmsg, &i2c_rpmsg, 2998+ rdata->adapter.nr, is_last); 2999+ if (ret < 0) { 3000+ mutex_unlock(&i2c_rpmsg.lock); 3001+ return ret; 3002+ } 3003+ 3004+ pmsg->len = ret; 3005+ } else { 3006+ ret = i2c_rpmsg_write(pmsg, &i2c_rpmsg, 3007+ rdata->adapter.nr, is_last); 3008+ if (ret < 0) { 3009+ mutex_unlock(&i2c_rpmsg.lock); 3010+ return ret; 3011+ } 3012+ } 3013+ } 3014+ 3015+ mutex_unlock(&i2c_rpmsg.lock); 3016+ return num; 3017+} 3018+ 3019+static u32 i2c_rpbus_func(struct i2c_adapter *a) 3020+{ 3021+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 3022+ | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 3023+} 3024+ 3025+static const struct i2c_algorithm i2c_rpbus_algorithm = { 3026+ .master_xfer = i2c_rpbus_xfer, 3027+ .functionality = i2c_rpbus_func, 3028+}; 3029+ 3030+static const struct i2c_adapter_quirks i2c_rpbus_quirks = { 3031+ .max_write_len = I2C_RPMSG_MAX_BUF_SIZE, 3032+ .max_read_len = I2C_RPMSG_MAX_BUF_SIZE, 3033+}; 3034+ 3035+static int i2c_rpbus_probe(struct platform_device *pdev) 3036+{ 3037+ struct device *dev = &pdev->dev; 3038+ struct device_node *np = dev->of_node; 3039+ struct imx_rpmsg_i2c_data *rdata; 3040+ struct i2c_adapter *adapter; 3041+ int ret; 3042+ 3043+ if (!i2c_rpmsg.rpdev) 3044+ return -EPROBE_DEFER; 3045+ 3046+ rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata), GFP_KERNEL); 3047+ if (!rdata) 3048+ return -ENOMEM; 3049+ 3050+ adapter = &rdata->adapter; 3051+ /* setup i2c adapter description */ 3052+ adapter->owner = THIS_MODULE; 3053+ adapter->class = I2C_CLASS_HWMON; 3054+ adapter->algo = &i2c_rpbus_algorithm; 3055+ adapter->dev.parent = dev; 3056+ adapter->dev.of_node = np; 3057+ adapter->nr = of_alias_get_id(np, "i2c"); 3058+ /* 3059+ * The driver will send the adapter->nr as BUS ID to the other 3060+ * side, and the other side will check the BUS ID to see whether 3061+ * the BUS has been registered. If there is alias id for this 3062+ * virtual adapter, linux kernel will automatically allocate one 3063+ * id which might be not the same number used in the other side, 3064+ * cause i2c slave probe failure under this virtual I2C bus. 3065+ * So let's add a BUG_ON to catch this issue earlier. 3066+ */ 3067+ BUG_ON(adapter->nr < 0); 3068+ adapter->quirks = &i2c_rpbus_quirks; 3069+ snprintf(rdata->adapter.name, sizeof(rdata->adapter.name), "%s", 3070+ "i2c-rpmsg-adapter"); 3071+ platform_set_drvdata(pdev, rdata); 3072+ 3073+ ret = i2c_add_adapter(&rdata->adapter); 3074+ if (ret < 0) { 3075+ dev_err(dev, "failed to add I2C adapter: %d\n", ret); 3076+ return ret; 3077+ } 3078+ 3079+ dev_info(dev, "add I2C adapter %s successfully\n", rdata->adapter.name); 3080+ 3081+ return 0; 3082+} 3083+ 3084+static int i2c_rpbus_remove(struct platform_device *pdev) 3085+{ 3086+ struct imx_rpmsg_i2c_data *rdata = platform_get_drvdata(pdev); 3087+ 3088+ i2c_del_adapter(&rdata->adapter); 3089+ 3090+ return 0; 3091+} 3092+ 3093+static const struct of_device_id imx_rpmsg_i2c_dt_ids[] = { 3094+ { .compatible = "fsl,i2c-rpbus", }, 3095+ { /* sentinel */ } 3096+}; 3097+MODULE_DEVICE_TABLE(of, imx_rpmsg_i2c_dt_ids); 3098+ 3099+static struct platform_driver imx_rpmsg_i2c_driver = { 3100+ .driver = { 3101+ .name = "imx_rpmsg_i2c", 3102+ .of_match_table = imx_rpmsg_i2c_dt_ids, 3103+ }, 3104+ .probe = i2c_rpbus_probe, 3105+ .remove = i2c_rpbus_remove 3106+}; 3107+ 3108+static int __init imx_rpmsg_i2c_driver_init(void) 3109+{ 3110+ int ret = 0; 3111+ 3112+ ret = register_rpmsg_driver(&i2c_rpmsg_driver); 3113+ if (ret < 0) 3114+ return ret; 3115+ 3116+ return platform_driver_register(&(imx_rpmsg_i2c_driver)); 3117+} 3118+subsys_initcall(imx_rpmsg_i2c_driver_init); 3119+ 3120+MODULE_AUTHOR("Clark Wang<xiaoning.wang@nxp.com>"); 3121+MODULE_DESCRIPTION("Driver for i2c over rpmsg"); 3122+MODULE_LICENSE("GPL v2"); 3123+MODULE_ALIAS("platform:i2c-rpbus"); 3124diff --git a/drivers/i2c/busses/xen-i2cfront.c b/drivers/i2c/busses/xen-i2cfront.c 3125new file mode 100644 3126index 000000000..6b8702074 3127--- /dev/null 3128+++ b/drivers/i2c/busses/xen-i2cfront.c 3129@@ -0,0 +1,507 @@ 3130+// SPDX-License-Identifier: GPL-2.0+ 3131+/* 3132+ * Copyright 2018 NXP 3133+ * 3134+ * Peng Fan <peng.fan@nxp.com> 3135+ */ 3136+ 3137+#include <linux/module.h> 3138+#include <linux/i2c.h> 3139+#include <linux/list.h> 3140+#include <linux/io.h> 3141+ 3142+#include <xen/xen.h> 3143+#include <xen/xenbus.h> 3144+#include <xen/grant_table.h> 3145+#include <xen/events.h> 3146+#include <xen/page.h> 3147+ 3148+#include <xen/interface/io/i2cif.h> 3149+ 3150+#define GRANT_INVALID_REF 0 3151+ 3152+struct i2cfront_info { 3153+ spinlock_t lock; 3154+ struct mutex xferlock; 3155+ struct i2c_adapter adapter; 3156+ struct xenbus_device *i2cdev; 3157+ int i2c_ring_ref; 3158+ struct i2cif_front_ring i2c_ring; 3159+ unsigned int evtchn; 3160+ unsigned int irq; 3161+ struct completion completion; 3162+ struct i2cif_request *req; 3163+ struct i2cif_response *res; 3164+}; 3165+ 3166+static void i2cfront_destroy_rings(struct i2cfront_info *info) 3167+{ 3168+ if (info->irq) 3169+ unbind_from_irqhandler(info->irq, info); 3170+ info->irq = 0; 3171+ 3172+ if (info->i2c_ring_ref != GRANT_INVALID_REF) { 3173+ gnttab_end_foreign_access(info->i2c_ring_ref, 0, 3174+ (unsigned long)info->i2c_ring.sring); 3175+ info->i2c_ring_ref = GRANT_INVALID_REF; 3176+ } 3177+ info->i2c_ring.sring = NULL; 3178+} 3179+ 3180+static int i2cfront_do_req(struct i2c_adapter *adapter, struct i2c_msg *msg, 3181+ int num) 3182+{ 3183+ struct i2cfront_info *info = i2c_get_adapdata(adapter); 3184+ struct i2cif_request *req; 3185+ struct i2cif_response *res; 3186+ int notify; 3187+ int ret; 3188+ RING_IDX i, rp; 3189+ int more_to_do = 0; 3190+ unsigned long flags; 3191+ int index; 3192+ 3193+ mutex_lock(&info->xferlock); 3194+ req = RING_GET_REQUEST(&info->i2c_ring, info->i2c_ring.req_prod_pvt); 3195+ 3196+ for (index = 0; index < num; index++) { 3197+ req->msg[index].addr = msg[index].addr; 3198+ req->msg[index].len = msg[index].len; 3199+ req->msg[index].flags = 0; 3200+ if (msg[index].flags & I2C_M_RD) 3201+ req->msg[index].flags |= I2CIF_M_RD; 3202+ if (msg[index].flags & I2C_M_TEN) 3203+ req->msg[index].flags |= I2CIF_M_TEN; 3204+ if (msg[index].flags & I2C_M_RECV_LEN) 3205+ req->msg[index].flags |= I2CIF_M_RECV_LEN; 3206+ if (msg[index].flags & I2C_M_NO_RD_ACK) 3207+ req->msg[index].flags |= I2CIF_M_NO_RD_ACK; 3208+ if (msg[index].flags & I2C_M_IGNORE_NAK) 3209+ req->msg[index].flags |= I2CIF_M_IGNORE_NAK; 3210+ if (msg[index].flags & I2C_M_REV_DIR_ADDR) 3211+ req->msg[index].flags |= I2CIF_M_REV_DIR_ADDR; 3212+ if (msg[index].flags & I2C_M_NOSTART) 3213+ req->msg[index].flags |= I2CIF_M_NOSTART; 3214+ if (msg[index].flags & I2C_M_STOP) 3215+ req->msg[index].flags |= I2CIF_M_STOP; 3216+ } 3217+ 3218+ req->num_msg = num; 3219+ req->is_smbus = false; 3220+ 3221+ if ((num == 2) && !(msg[0].flags & I2C_M_RD) && 3222+ (msg[1].flags & I2C_M_RD)) { 3223+ memcpy(req->write_buf, msg[0].buf, 3224+ min_t(int, msg[0].len, I2CIF_BUF_LEN)); 3225+ } else if (num == 1) { 3226+ if (!(msg->flags & I2C_M_RD)) 3227+ memcpy(req->write_buf, msg->buf, 3228+ min_t(int, msg->len, I2CIF_BUF_LEN)); 3229+ } else { 3230+ dev_err(&adapter->dev, "%s not supported\n", __func__); 3231+ return -EIO; 3232+ } 3233+ 3234+ spin_lock(&info->lock); 3235+ info->i2c_ring.req_prod_pvt++; 3236+ RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(&info->i2c_ring, notify); 3237+ spin_unlock(&info->lock); 3238+ if (notify) 3239+ notify_remote_via_irq(info->irq); 3240+ 3241+ wait_for_completion(&info->completion); 3242+ 3243+ spin_lock_irqsave(&info->lock, flags); 3244+ rp = info->i2c_ring.sring->rsp_prod; 3245+ rmb(); /* ensure we see queued responses up to "rp" */ 3246+ 3247+ ret = -EIO; 3248+ for (i = info->i2c_ring.rsp_cons; i != rp; i++) { 3249+ res = RING_GET_RESPONSE(&info->i2c_ring, i); 3250+ if ((num == 2) && !(msg[0].flags & I2C_M_RD) && 3251+ (msg[1].flags & I2C_M_RD)) { 3252+ memcpy(msg[1].buf, res->read_buf, 3253+ min_t(int, msg[1].len, I2CIF_BUF_LEN)); 3254+ } else if (num == 1) { 3255+ if (!(msg->flags & I2C_M_RD)) 3256+ memcpy(msg->buf, res->read_buf, 3257+ min_t(int, msg->len, I2CIF_BUF_LEN)); 3258+ } 3259+ 3260+ ret = res->result; 3261+ } 3262+ 3263+ info->i2c_ring.rsp_cons = i; 3264+ 3265+ if (i != info->i2c_ring.req_prod_pvt) 3266+ RING_FINAL_CHECK_FOR_RESPONSES(&info->i2c_ring, more_to_do); 3267+ else 3268+ info->i2c_ring.sring->rsp_event = i + 1; 3269+ 3270+ spin_unlock_irqrestore(&info->lock, flags); 3271+ 3272+ mutex_unlock(&info->xferlock); 3273+ 3274+ return ret; 3275+} 3276+ 3277+int i2cfront_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 3278+{ 3279+ struct i2cfront_info *info = i2c_get_adapdata(adapter); 3280+ int ret, i; 3281+ 3282+ if (!info || !info->i2cdev) { 3283+ dev_err(&adapter->dev, "Not initialized\n"); 3284+ return -EIO; 3285+ } 3286+ 3287+ if (info->i2cdev->state != XenbusStateConnected) { 3288+ dev_err(&adapter->dev, "Not connected\n"); 3289+ return -EIO; 3290+ } 3291+ 3292+ for (i = 0; i < num; i++) { 3293+ if (msgs[i].flags & I2C_M_RD) { 3294+ ret = i2cfront_do_req(adapter, &msgs[i], 1); 3295+ } else if ((i + 1 < num) && (msgs[i + 1].flags & I2C_M_RD) && 3296+ (msgs[i].addr == msgs[i + 1].addr)) { 3297+ ret = i2cfront_do_req(adapter, &msgs[i], 2); 3298+ i++; 3299+ } else { 3300+ ret = i2cfront_do_req(adapter, &msgs[i], 1); 3301+ } 3302+ 3303+ if (ret < 0) 3304+ goto err; 3305+ } 3306+err: 3307+ return (ret < 0) ? ret : num; 3308+} 3309+ 3310+static int i2cfront_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 3311+ unsigned short flags, char read_write, 3312+ u8 command, int size, union i2c_smbus_data *data) 3313+{ 3314+ struct i2cfront_info *info = i2c_get_adapdata(adapter); 3315+ struct i2cif_response *res; 3316+ struct i2cif_request *req; 3317+ unsigned long lock_flags; 3318+ int more_to_do = 0; 3319+ RING_IDX i, rp; 3320+ int notify; 3321+ int ret; 3322+ 3323+ if (!info || !info->i2cdev) { 3324+ dev_err(&adapter->dev, "Not initialized\n"); 3325+ return -EIO; 3326+ } 3327+ 3328+ if (info->i2cdev->state != XenbusStateConnected) { 3329+ dev_err(&adapter->dev, "Not connected\n"); 3330+ return -EIO; 3331+ } 3332+ 3333+ mutex_lock(&info->xferlock); 3334+ req = RING_GET_REQUEST(&info->i2c_ring, info->i2c_ring.req_prod_pvt); 3335+ 3336+ req->is_smbus = true; 3337+ req->addr = addr; 3338+ req->flags = flags; 3339+ req->read_write = read_write; 3340+ req->command = command; 3341+ req->protocol = size; 3342+ if (data != NULL) 3343+ memcpy(&req->write_buf, data, sizeof(union i2c_smbus_data)); 3344+ 3345+ spin_lock(&info->lock); 3346+ info->i2c_ring.req_prod_pvt++; 3347+ RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(&info->i2c_ring, notify); 3348+ spin_unlock(&info->lock); 3349+ if (notify) 3350+ notify_remote_via_irq(info->irq); 3351+ 3352+ wait_for_completion(&info->completion); 3353+ 3354+ spin_lock_irqsave(&info->lock, lock_flags); 3355+ rp = info->i2c_ring.sring->rsp_prod; 3356+ rmb(); /* ensure we see queued responses up to "rp" */ 3357+ 3358+ ret = -EIO; 3359+ for (i = info->i2c_ring.rsp_cons; i != rp; i++) { 3360+ res = RING_GET_RESPONSE(&info->i2c_ring, i); 3361+ 3362+ if (data != NULL && read_write == I2C_SMBUS_READ) 3363+ memcpy(data, &res->read_buf, sizeof(union i2c_smbus_data)); 3364+ 3365+ ret = res->result; 3366+ } 3367+ 3368+ info->i2c_ring.rsp_cons = i; 3369+ 3370+ if (i != info->i2c_ring.req_prod_pvt) 3371+ RING_FINAL_CHECK_FOR_RESPONSES(&info->i2c_ring, more_to_do); 3372+ else 3373+ info->i2c_ring.sring->rsp_event = i + 1; 3374+ 3375+ spin_unlock_irqrestore(&info->lock, lock_flags); 3376+ 3377+ mutex_unlock(&info->xferlock); 3378+ 3379+ return ret; 3380+} 3381+ 3382+static u32 i2cfront_func(struct i2c_adapter *adapter) 3383+{ 3384+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_BYTE_DATA | 3385+ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_QUICK | 3386+ I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_I2C_BLOCK; 3387+} 3388+ 3389+static const struct i2c_algorithm i2cfront_algo = { 3390+ .master_xfer = i2cfront_xfer, 3391+ .smbus_xfer = i2cfront_smbus_xfer, 3392+ .functionality = i2cfront_func, 3393+}; 3394+ 3395+static int i2cfront_probe(struct xenbus_device *dev, 3396+ const struct xenbus_device_id *id) 3397+{ 3398+ struct i2cfront_info *info; 3399+ 3400+ info = kzalloc(sizeof(struct i2cfront_info), GFP_KERNEL); 3401+ if (!info) 3402+ return -ENOMEM; 3403+ 3404+ info->i2cdev = dev; 3405+ dev_set_drvdata(&dev->dev, info); 3406+ info->adapter.owner = THIS_MODULE; 3407+ info->adapter.algo = &i2cfront_algo; 3408+ info->adapter.dev.parent = &dev->dev; 3409+ strlcpy(info->adapter.name, dev->nodename, sizeof(info->adapter.name)); 3410+ i2c_set_adapdata(&info->adapter, info); 3411+ spin_lock_init(&info->lock); 3412+ mutex_init(&info->xferlock); 3413+ init_completion(&info->completion); 3414+ 3415+ return 0; 3416+} 3417+ 3418+static int i2cfront_handle_int(struct i2cfront_info *info) 3419+{ 3420+ complete(&info->completion); 3421+ 3422+ return 0; 3423+} 3424+ 3425+static irqreturn_t i2cfront_int(int irq, void *dev_id) 3426+{ 3427+ struct i2cfront_info *info = dev_id; 3428+ 3429+ while (i2cfront_handle_int(info)) 3430+ cond_resched(); 3431+ 3432+ return IRQ_HANDLED; 3433+} 3434+ 3435+static int i2cfront_setup_rings(struct xenbus_device *dev, 3436+ struct i2cfront_info *info) 3437+{ 3438+ struct i2cif_sring *i2c_sring; 3439+ grant_ref_t gref; 3440+ int err; 3441+ 3442+ info->i2c_ring_ref = GRANT_INVALID_REF; 3443+ i2c_sring = (struct i2cif_sring *)get_zeroed_page(GFP_NOIO | 3444+ __GFP_HIGH); 3445+ if (!i2c_sring) { 3446+ xenbus_dev_fatal(dev, -ENOMEM, "allocating i2c sring"); 3447+ return -ENOMEM; 3448+ } 3449+ 3450+ SHARED_RING_INIT(i2c_sring); 3451+ FRONT_RING_INIT(&info->i2c_ring, i2c_sring, PAGE_SIZE); 3452+ 3453+ err = xenbus_grant_ring(dev, i2c_sring, 1, &gref); 3454+ if (err < 0) { 3455+ free_page((unsigned long)i2c_sring); 3456+ info->i2c_ring.sring = NULL; 3457+ goto fail; 3458+ } 3459+ info->i2c_ring_ref = gref; 3460+ 3461+ err = xenbus_alloc_evtchn(dev, &info->evtchn); 3462+ if (err) { 3463+ xenbus_dev_fatal(dev, err, "xenbus_alloc_evtchn"); 3464+ goto fail; 3465+ } 3466+ 3467+ err = bind_evtchn_to_irqhandler(info->evtchn, i2cfront_int, 0, 3468+ "xen_i2cif", info); 3469+ if (err <= 0) { 3470+ xenbus_dev_fatal(dev, err, "bind_evtchn_to_irqhandler failed"); 3471+ goto fail; 3472+ } 3473+ 3474+ info->irq = err; 3475+ 3476+ return 0; 3477+ 3478+fail: 3479+ i2cfront_destroy_rings(info); 3480+ return err; 3481+} 3482+ 3483+static int i2cfront_connect(struct xenbus_device *dev) 3484+{ 3485+ struct i2cfront_info *info = dev_get_drvdata(&dev->dev); 3486+ struct xenbus_transaction xbt; 3487+ struct device_node *np; 3488+ const char *be_adapter; 3489+ char xenstore_adapter[I2CIF_ADAPTER_NAME_LEN]; 3490+ char *message; 3491+ int err; 3492+ 3493+ err = i2cfront_setup_rings(dev, info); 3494+ if (err) { 3495+ dev_err(&dev->dev, "%s:failure....", __func__); 3496+ return err; 3497+ } 3498+again: 3499+ err = xenbus_transaction_start(&xbt); 3500+ if (err) { 3501+ xenbus_dev_fatal(dev, err, "starting transaction"); 3502+ goto destroy_ring; 3503+ } 3504+ 3505+ err = xenbus_printf(xbt, dev->nodename, "ring-ref", "%u", 3506+ info->i2c_ring_ref); 3507+ if (err) { 3508+ message = "writing i2c ring-ref"; 3509+ goto abort_transaction; 3510+ } 3511+ 3512+ err = xenbus_printf(xbt, dev->nodename, "event-channel", "%u", 3513+ info->evtchn); 3514+ if (err) { 3515+ message = "writing event-channel"; 3516+ goto abort_transaction; 3517+ } 3518+ 3519+ err = xenbus_scanf(xbt, dev->nodename, 3520+ "be-adapter", "%32s", xenstore_adapter); 3521+ if (err != 1) { 3522+ message = "getting be-adapter"; 3523+ goto abort_transaction; 3524+ } 3525+ 3526+ err = xenbus_transaction_end(xbt, 0); 3527+ if (err) { 3528+ if (err == -EAGAIN) 3529+ goto again; 3530+ xenbus_dev_fatal(dev, err, "completing transaction"); 3531+ goto destroy_ring; 3532+ } 3533+ 3534+ for_each_compatible_node(np, NULL, "xen,i2c") { 3535+ err = of_property_read_string(np, "be-adapter", &be_adapter); 3536+ if (err) 3537+ continue; 3538+ if (!strncmp(xenstore_adapter, be_adapter, 3539+ I2CIF_ADAPTER_NAME_LEN)) { 3540+ info->adapter.dev.of_node = np; 3541+ break; 3542+ } 3543+ } 3544+ 3545+ err = i2c_add_adapter(&info->adapter); 3546+ if (err) 3547+ return err; 3548+ 3549+ dev_info(&info->adapter.dev, "XEN I2C adapter registered\n"); 3550+ 3551+ return 0; 3552+ 3553+abort_transaction: 3554+ xenbus_transaction_end(xbt, 1); 3555+ xenbus_dev_fatal(dev, err, "%s", message); 3556+ 3557+destroy_ring: 3558+ i2cfront_destroy_rings(info); 3559+ 3560+ return err; 3561+} 3562+ 3563+static void i2cfront_disconnect(struct xenbus_device *dev) 3564+{ 3565+ pr_info("%s\n", __func__); 3566+ xenbus_frontend_closed(dev); 3567+} 3568+ 3569+static void i2cfront_backend_changed(struct xenbus_device *dev, 3570+ enum xenbus_state backend_state) 3571+{ 3572+ switch (backend_state) { 3573+ case XenbusStateInitialising: 3574+ case XenbusStateReconfiguring: 3575+ case XenbusStateReconfigured: 3576+ case XenbusStateUnknown: 3577+ break; 3578+ 3579+ case XenbusStateInitWait: 3580+ case XenbusStateInitialised: 3581+ case XenbusStateConnected: 3582+ if (dev->state != XenbusStateInitialising) 3583+ break; 3584+ if (!i2cfront_connect(dev)) 3585+ xenbus_switch_state(dev, XenbusStateConnected); 3586+ break; 3587+ 3588+ case XenbusStateClosed: 3589+ if (dev->state == XenbusStateClosed) 3590+ break; 3591+ i2cfront_disconnect(dev); 3592+ break; 3593+ case XenbusStateClosing: 3594+ i2cfront_disconnect(dev); 3595+ break; 3596+ 3597+ default: 3598+ xenbus_dev_fatal(dev, -EINVAL, "saw state %d at frontend", 3599+ backend_state); 3600+ break; 3601+ } 3602+} 3603+ 3604+static int i2cfront_remove(struct xenbus_device *dev) 3605+{ 3606+ struct i2cfront_info *info = dev_get_drvdata(&dev->dev); 3607+ 3608+ i2c_del_adapter(&info->adapter); 3609+ i2cfront_destroy_rings(info); 3610+ 3611+ kfree(info); 3612+ 3613+ dev_info(&dev->dev, "Remove"); 3614+ return 0; 3615+} 3616+ 3617+static const struct xenbus_device_id i2cfront_ids[] = { 3618+ { "vi2c" }, 3619+ { "" }, 3620+}; 3621+ 3622+static struct xenbus_driver i2cfront_driver = { 3623+ .ids = i2cfront_ids, 3624+ .probe = i2cfront_probe, 3625+ .otherend_changed = i2cfront_backend_changed, 3626+ .remove = i2cfront_remove, 3627+}; 3628+ 3629+static int __init i2cfront_init(void) 3630+{ 3631+ if (!xen_domain()) 3632+ return -ENODEV; 3633+ 3634+ return xenbus_register_frontend(&i2cfront_driver); 3635+} 3636+subsys_initcall(i2cfront_init); 3637diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c 3638index 4ad665757..e9d6b12ec 100644 3639--- a/drivers/i2c/muxes/i2c-mux-pca954x.c 3640+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c 3641@@ -59,6 +59,7 @@ enum pca_type { 3642 pca_9546, 3643 pca_9547, 3644 pca_9548, 3645+ pca_9646, 3646 pca_9846, 3647 pca_9847, 3648 pca_9848, 3649@@ -140,6 +141,11 @@ static const struct chip_desc chips[] = { 3650 .muxtype = pca954x_isswi, 3651 .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, 3652 }, 3653+ [pca_9646] = { 3654+ .nchans = 4, 3655+ .muxtype = pca954x_isswi, 3656+ .id = { .manufacturer_id = I2C_DEVICE_ID_NONE }, 3657+ }, 3658 [pca_9846] = { 3659 .nchans = 4, 3660 .muxtype = pca954x_isswi, 3661@@ -185,6 +191,7 @@ static const struct i2c_device_id pca954x_id[] = { 3662 { "pca9546", pca_9546 }, 3663 { "pca9547", pca_9547 }, 3664 { "pca9548", pca_9548 }, 3665+ { "pca9646", pca_9646 }, 3666 { "pca9846", pca_9846 }, 3667 { "pca9847", pca_9847 }, 3668 { "pca9848", pca_9848 }, 3669@@ -202,6 +209,7 @@ static const struct of_device_id pca954x_of_match[] = { 3670 { .compatible = "nxp,pca9546", .data = &chips[pca_9546] }, 3671 { .compatible = "nxp,pca9547", .data = &chips[pca_9547] }, 3672 { .compatible = "nxp,pca9548", .data = &chips[pca_9548] }, 3673+ { .compatible = "nxp,pca9646", .data = &chips[pca_9646] }, 3674 { .compatible = "nxp,pca9846", .data = &chips[pca_9846] }, 3675 { .compatible = "nxp,pca9847", .data = &chips[pca_9847] }, 3676 { .compatible = "nxp,pca9848", .data = &chips[pca_9848] }, 3677