1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __LINUX_KVM_LOONGARCH_H 20 #define __LINUX_KVM_LOONGARCH_H 21 #include <linux/types.h> 22 #include <stdint.h> 23 #define __KVM_HAVE_GUEST_DEBUG 24 #define KVM_GUESTDBG_USE_SW_BP 0x00010000 25 #define KVM_GUESTDBG_USE_HW_BP 0x00020000 26 #define KVM_DATA_HW_BREAKPOINT_NUM 8 27 #define KVM_INST_HW_BREAKPOINT_NUM 8 28 #define __KVM_HAVE_READONLY_MEM 29 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 30 struct kvm_regs { 31 __u64 gpr[32]; 32 __u64 pc; 33 }; 34 struct kvm_cpucfg { 35 __u32 cpucfg[64]; 36 }; 37 struct kvm_fpu { 38 __u32 fcsr; 39 __u32 none; 40 __u64 fcc; 41 struct kvm_fpureg { 42 __u64 val64[4]; 43 } fpr[32]; 44 }; 45 #define KVM_REG_LOONGARCH_GP (KVM_REG_LOONGARCH | 0x00000ULL) 46 #define KVM_REG_LOONGARCH_CSR (KVM_REG_LOONGARCH | 0x10000ULL) 47 #define KVM_REG_LOONGARCH_KVM (KVM_REG_LOONGARCH | 0x20000ULL) 48 #define KVM_REG_LOONGARCH_FPU (KVM_REG_LOONGARCH | 0x30000ULL) 49 #define KVM_REG_LOONGARCH_MASK (KVM_REG_LOONGARCH | 0x30000ULL) 50 #define KVM_CSR_IDX_MASK (0x10000 - 1) 51 #define KVM_REG_LOONGARCH_COUNTER (KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 3) 52 #define KVM_REG_LOONGARCH_VCPU_RESET (KVM_REG_LOONGARCH_KVM | KVM_REG_SIZE_U64 | 4) 53 #define __KVM_HAVE_IRQ_LINE 54 struct kvm_debug_exit_arch { 55 __u64 era; 56 __u32 fwps; 57 __u32 mwps; 58 __u32 exception; 59 }; 60 struct hw_breakpoint { 61 __u64 addr; 62 __u64 mask; 63 __u32 asid; 64 __u32 ctrl; 65 }; 66 struct kvm_guest_debug_arch { 67 struct hw_breakpoint data_breakpoint[KVM_DATA_HW_BREAKPOINT_NUM]; 68 struct hw_breakpoint inst_breakpoint[KVM_INST_HW_BREAKPOINT_NUM]; 69 int inst_bp_nums, data_bp_nums; 70 }; 71 struct kvm_sync_regs { 72 }; 73 struct kvm_sregs { 74 }; 75 struct kvm_iocsr_entry { 76 __u32 addr; 77 __u32 pad; 78 __u64 data; 79 }; 80 struct kvm_csr_entry { 81 __u32 index; 82 __u32 reserved; 83 __u64 data; 84 }; 85 struct kvm_msrs { 86 __u32 ncsrs; 87 __u32 pad; 88 struct kvm_csr_entry entries[0]; 89 }; 90 struct kvm_loongarch_interrupt { 91 __u32 cpu; 92 __u32 irq; 93 }; 94 #define KVM_IRQCHIP_LS7A_IOAPIC 0x0 95 #define KVM_IRQCHIP_LS3A_GIPI 0x1 96 #define KVM_IRQCHIP_LS3A_HT_IRQ 0x2 97 #define KVM_IRQCHIP_LS3A_ROUTE 0x3 98 #define KVM_IRQCHIP_LS3A_EXTIRQ 0x4 99 #define KVM_IRQCHIP_LS3A_IPMASK 0x5 100 #define KVM_NR_IRQCHIPS 1 101 #define KVM_IRQCHIP_NUM_PINS 64 102 #define KVM_MAX_CORES 256 103 #define KVM_EXTIOI_IRQS (256) 104 #define KVM_EXTIOI_IRQS_BITMAP_SIZE (KVM_EXTIOI_IRQS / 8) 105 #define KVM_EXTIOI_IRQS_IPMAP_SIZE (KVM_EXTIOI_IRQS / 32) 106 #define KVM_EXTIOI_IRQS_PER_GROUP 32 107 #define KVM_EXTIOI_IRQS_COREMAP_SIZE (KVM_EXTIOI_IRQS) 108 #define KVM_EXTIOI_IRQS_NODETYPE_SIZE 16 109 struct ls7a_ioapic_state { 110 __u64 int_id; 111 __u64 int_mask; 112 __u64 htmsi_en; 113 __u64 intedge; 114 __u64 intclr; 115 __u64 auto_crtl0; 116 __u64 auto_crtl1; 117 __u8 route_entry[64]; 118 __u8 htmsi_vector[64]; 119 __u64 intisr_chip0; 120 __u64 intisr_chip1; 121 __u64 last_intirr; 122 __u64 intirr; 123 __u64 intisr; 124 __u64 int_polarity; 125 }; 126 struct loongarch_gipi_single { 127 __u32 status; 128 __u32 en; 129 __u32 set; 130 __u32 clear; 131 __u64 buf[4]; 132 }; 133 struct loongarch_gipiState { 134 struct loongarch_gipi_single core[KVM_MAX_CORES]; 135 }; 136 struct kvm_loongarch_ls3a_extirq_state { 137 union ext_en_r { 138 uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8]; 139 uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4]; 140 uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE]; 141 } ext_en_r; 142 union bounce_r { 143 uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8]; 144 uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4]; 145 uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE]; 146 } bounce_r; 147 union ext_isr_r { 148 uint64_t reg_u64[KVM_EXTIOI_IRQS_BITMAP_SIZE / 8]; 149 uint32_t reg_u32[KVM_EXTIOI_IRQS_BITMAP_SIZE / 4]; 150 uint8_t reg_u8[KVM_EXTIOI_IRQS_BITMAP_SIZE]; 151 } ext_isr_r; 152 union ext_core_isr_r { 153 uint64_t reg_u64[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE / 8]; 154 uint32_t reg_u32[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE / 4]; 155 uint8_t reg_u8[KVM_MAX_CORES][KVM_EXTIOI_IRQS_BITMAP_SIZE]; 156 } ext_core_isr_r; 157 union ip_map_r { 158 uint64_t reg_u64; 159 uint32_t reg_u32[KVM_EXTIOI_IRQS_IPMAP_SIZE / 4]; 160 uint8_t reg_u8[KVM_EXTIOI_IRQS_IPMAP_SIZE]; 161 } ip_map_r; 162 union core_map_r { 163 uint64_t reg_u64[KVM_EXTIOI_IRQS_COREMAP_SIZE / 8]; 164 uint32_t reg_u32[KVM_EXTIOI_IRQS_COREMAP_SIZE / 4]; 165 uint8_t reg_u8[KVM_EXTIOI_IRQS_COREMAP_SIZE]; 166 } core_map_r; 167 union node_type_r { 168 uint64_t reg_u64[KVM_EXTIOI_IRQS_NODETYPE_SIZE / 4]; 169 uint32_t reg_u32[KVM_EXTIOI_IRQS_NODETYPE_SIZE / 2]; 170 uint16_t reg_u16[KVM_EXTIOI_IRQS_NODETYPE_SIZE]; 171 uint8_t reg_u8[KVM_EXTIOI_IRQS_NODETYPE_SIZE * 2]; 172 } node_type_r; 173 }; 174 struct loongarch_kvm_irqchip { 175 __u16 chip_id; 176 __u16 len; 177 __u16 vcpu_id; 178 __u16 reserved; 179 char data[0]; 180 }; 181 #endif 182