Lines Matching full:operand
90 void AssemblerAarch64::Ldp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Ldp() argument
93 if (operand.IsImmediateOffset()) { in Ldp()
94 switch (operand.GetAddrMode()) { in Ldp()
109 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
116 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldp()
124 void AssemblerAarch64::Stp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Stp() argument
127 if (operand.IsImmediateOffset()) { in Stp()
128 switch (operand.GetAddrMode()) { in Stp()
143 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
150 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stp()
158 …blerAarch64::Ldp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Ldp() argument
161 if (operand.IsImmediateOffset()) { in Ldp()
162 switch (operand.GetAddrMode()) { in Ldp()
176 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
196 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Ldp()
204 …blerAarch64::Stp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Stp() argument
207 if (operand.IsImmediateOffset()) { in Stp()
208 switch (operand.GetAddrMode()) { in Stp()
222 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
242 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Stp()
277 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand, Scale scale) in Ldr() argument
280 uint32_t op = GetOpcodeOfLdr(operand, scale); in Ldr()
281 if (operand.IsImmediateOffset()) { in Ldr()
282 uint64_t imm = GetImmOfLdr(operand, scale, regX); in Ldr()
283 bool isSigned = operand.GetAddrMode() != AddrMode::OFFSET; in Ldr()
286 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldr()
289 ASSERT(operand.GetExtendOption() != Extend::NO_EXTEND); in Ldr()
290 uint32_t shift = GetShiftOfLdr(operand, scale, regX); in Ldr()
291 Register rm = operand.GetRegisterOffset(); in Ldr()
292 Register rn = operand.GetRegBase(); in Ldr()
294 (operand.GetExtendOption() << LDR_STR_Extend_LOWBITS) & LDR_STR_Extend_MASK; in Ldr()
303 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand) in Ldr() argument
305 Ldr(rt, operand, Scale::Q); in Ldr()
308 void AssemblerAarch64::Ldrh(const Register &rt, const MemoryOperand &operand) in Ldrh() argument
311 Ldr(rt, operand, Scale::H); in Ldrh()
314 void AssemblerAarch64::Ldrb(const Register &rt, const MemoryOperand &operand) in Ldrb() argument
317 Ldr(rt, operand, Scale::B); in Ldrb()
320 void AssemblerAarch64::Str(const Register &rt, const MemoryOperand &operand) in Str() argument
325 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Str()
326 if (operand.IsImmediateOffset()) { in Str()
327 switch (operand.GetAddrMode()) { in Str()
349 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Str()
357 void AssemblerAarch64::Ldur(const Register &rt, const MemoryOperand &operand) in Ldur() argument
361 ASSERT(operand.IsImmediateOffset()); in Ldur()
362 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldur()
365 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldur()
369 void AssemblerAarch64::Stur(const Register &rt, const MemoryOperand &operand) in Stur() argument
373 ASSERT(operand.IsImmediateOffset()); in Stur()
374 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stur()
377 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stur()
462 Add(rd, rm, Operand(Immediate(0))); in Mov()
464 Orr(rd, Register(Zero), Operand(rm)); in Mov()
633 …firstshift = (tz / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
635 …lastshift = ((63 - lz) / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
648 … firstshift += 16; // 16 : 16 means the operand of MOVK is 16 bits Immediate in EmitMovInstruct()
697 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand) in Orr() argument
699 ASSERT(operand.IsShifted()); in Orr()
700 BitWiseOpShift(ORR_Shift, rd, rn, operand); in Orr()
703 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand) in And() argument
705 ASSERT(operand.IsShifted()); in And()
706 BitWiseOpShift(AND_Shift, rd, rn, operand); in And()
709 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand) in Ands() argument
711 ASSERT(operand.IsShifted()); in Ands()
712 BitWiseOpShift(ANDS_Shift, rd, rn, operand); in Ands()
721 …4::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand) in BitWiseOpShift() argument
723 …uint32_t shift_field = (operand.GetShiftOption() << BITWISE_OP_Shift_LOWBITS) & BITWISE_OP_Shift_M… in BitWiseOpShift()
724 …uint32_t shift_amount = (operand.GetShiftAmount() << BITWISE_OP_ShiftAmount_LOWBITS) & BITWISE_OP_… in BitWiseOpShift()
725 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) | in BitWiseOpShift()
777 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand) in Add() argument
779 if (operand.IsImmediate()) { in Add()
780 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Add()
787 if (operand.IsShifted()) { in Add()
788 AddSubReg(ADD_Shift, rd, rn, false, operand); in Add()
790 AddSubReg(ADD_Extend, rd, rn, false, operand); in Add()
795 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand) in Adds() argument
797 if (operand.IsImmediate()) { in Adds()
798 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue()); in Adds()
800 if (operand.IsShifted()) { in Adds()
801 AddSubReg(ADD_Shift, rd, rn, true, operand); in Adds()
803 AddSubReg(ADD_Extend, rd, rn, true, operand); in Adds()
808 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand) in Sub() argument
810 if (operand.IsImmediate()) { in Sub()
811 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Sub()
818 if (operand.IsShifted()) { in Sub()
819 AddSubReg(SUB_Shift, rd, rn, false, operand); in Sub()
821 AddSubReg(SUB_Extend, rd, rn, false, operand); in Sub()
826 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand) in Subs() argument
828 if (operand.IsImmediate()) { in Subs()
829 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue()); in Subs()
831 if (operand.IsShifted()) { in Subs()
832 AddSubReg(SUB_Shift, rd, rn, true, operand); in Subs()
834 AddSubReg(SUB_Extend, rd, rn, true, operand); in Subs()
871 bool setFlags, const Operand &operand) in AddSubReg() argument
875 if (operand.IsShifted()) { in AddSubReg()
876 … uint32_t shift_field = ((operand.GetShiftOption()) << ADD_SUB_Shift_LOWBITS) & ADD_SUB_Shift_MASK; in AddSubReg()
877 …uint32_t shift_amount = ((operand.GetShiftAmount()) << ADD_SUB_ShiftAmount_LOWBITS) & ADD_SUB_Shif… in AddSubReg()
879 code = Sf(!rd.IsW()) | op | flags_field | shift_field | Rm(operand.Reg().GetId()) | in AddSubReg()
884 (operand.GetExtendOption() << ADD_SUB_ExtendOption_LOWBITS) & ADD_SUB_ExtendOption_MASK; in AddSubReg()
885 …uint32_t extend_shift = (operand.GetShiftAmount() << ADD_SUB_ExtendShift_LOWBITS) & ADD_SUB_Extend… in AddSubReg()
886 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field | in AddSubReg()
892 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand) in Cmp() argument
894 Subs(Register(Zero, rd.GetType()), rd, operand); in Cmp()
897 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Conditi… in CMov() argument
899 ASSERT(!operand.IsImmediate()); in CMov()
901 …uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | R… in CMov()
1144 uint64_t AssemblerAarch64::GetImmOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetImmOfLdr() argument
1146 ASSERT(operand.IsImmediateOffset()); in GetImmOfLdr()
1147 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in GetImmOfLdr()
1148 if (operand.GetAddrMode() == OFFSET) { in GetImmOfLdr()
1162 uint64_t AssemblerAarch64::GetOpcodeOfLdr(const MemoryOperand &operand, Scale scale) in GetOpcodeOfLdr() argument
1165 if (operand.IsImmediateOffset()) { in GetOpcodeOfLdr()
1166 switch (operand.GetAddrMode()) { in GetOpcodeOfLdr()
1225 uint32_t AssemblerAarch64::GetShiftOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetShiftOfLdr() argument
1229 shift = operand.GetShiftOption() != Shift::NO_SHIFT; in GetShiftOfLdr()
1231 shift = operand.GetShiftAmount(); in GetShiftOfLdr()
1235 shift = operand.GetShiftAmount(); in GetShiftOfLdr()