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Lines Matching full:acc

49     GateAccessor acc(const_cast<Circuit*>(circuit));  in CalculateDominatorTree()  local
56 auto startGate = acc.GetStateRoot(); in CalculateDominatorTree()
57 acc.SetMark(startGate, MarkCode::VISITED); in CalculateDominatorTree()
64 if (acc.GetOpCode(curGate) != OpCode::LOOP_BACK) { in CalculateDominatorTree()
65 auto uses = acc.Uses(curGate); in CalculateDominatorTree()
67 if (useIt.GetIndex() < acc.GetStateCount(*useIt) && in CalculateDominatorTree()
68 acc.IsState(*useIt) && acc.GetMark(*useIt) == MarkCode::NO_MARK) { in CalculateDominatorTree()
69 acc.SetMark(*useIt, MarkCode::VISITED); in CalculateDominatorTree()
97 acc.GetInStates(bbGatesList[idx], preGates); in CalculateDominatorTree()
133 GateAccessor acc(const_cast<Circuit*>(circuit)); in Run() local
215 acc.GetOuts(acc.GetArgRoot(), argList); in Run()
217 return acc.TryGetValue(lhs) > acc.TryGetValue(rhs); in Run()
223 auto uses = acc.Uses(bbGate); in Run()
226 if (acc.IsFixed(succGate)) { in Run()
227 result[bbGatesAddrToIdx.at(acc.GetIn(succGate, 0))].push_back(succGate); in Run()
243 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingUpperBound() local
258 } else if (acc.IsProlog(gate) || acc.IsRoot(gate) || acc.IsVirtualState(gate)) { in CalculateSchedulingUpperBound()
261 } else if (acc.IsFixed(gate)) { in CalculateSchedulingUpperBound()
262 returnValue = bbGatesAddrToIdx.at(acc.GetIn(gate, 0)); in CalculateSchedulingUpperBound()
264 } else if (acc.IsState(gate)) { in CalculateSchedulingUpperBound()
283 acc.GetIns(schedulableGate, rootPredGates); in CalculateSchedulingUpperBound()
322 acc.GetIns(predGate, newPredGates); in CalculateSchedulingUpperBound()
347 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateFixedGatesList() local
350 auto uses = acc.Uses(item.first); in CalculateFixedGatesList()
353 if (acc.IsFixed(succGate)) { in CalculateFixedGatesList()
366 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingLowerBound() local
380 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
390 if (!acc.IsSchedulable(prevGate)) { in CalculateSchedulingLowerBound()
399 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
416 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
427 if (!acc.IsSchedulable(prevGate)) { in CalculateSchedulingLowerBound()
433 if (acc.IsState(curGate)) { // cur_opcode would not be STATE_ENTRY in CalculateSchedulingLowerBound()
435 } else if (acc.IsSelector(curGate)) { in CalculateSchedulingLowerBound()
437 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(acc.GetIn(curGate, 0), idx - 1)); in CalculateSchedulingLowerBound()
438 } else if (acc.IsFixed(curGate)) { in CalculateSchedulingLowerBound()
440 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(curGate, 0)); in CalculateSchedulingLowerBound()
457 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
466 GateAccessor acc(const_cast<Circuit*>(circuit)); in Print() local
473 auto opcode = acc.GetOpCode((*cfg)[bbIdx].front()); in Print()
479 auto ins = acc.Ins(head); in Print()
482 if (acc.IsState(predState) || in Print()
483 acc.GetOpCode(predState) == OpCode::STATE_ENTRY) { in Print()
491 auto uses = acc.Uses(h); in Print()
494 if (acc.IsState(succState) || in Print()
495 acc.GetOpCode(succState) == OpCode::STATE_ENTRY) { in Print()
502 acc.Print((*cfg)[bbIdx][instIdx - 1]); in Print()