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1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
29 so that swapping, page migration, page merging, transparent
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
37 - reliability:
44 pfn host page frame number
52 pte page table entry (used also to refer generically to paging structure
62 The mmu supports first-generation mmu hardware, which allows an atomic switch
64 two-dimensional paging (AMD's NPT and Intel's EPT). The emulated hardware
65 it exposes is the traditional 2/3/4 level x86 mmu, with support for global
76 - when guest paging is disabled, we translate guest physical addresses to
77 host physical addresses (gpa->hpa)
78 - when guest paging is enabled, we translate guest virtual addresses, to
79 guest physical addresses, to host physical addresses (gva->gpa->hpa)
80 - when the guest launches a guest of its own, we translate nested guest
82 addresses, to host physical addresses (ngva->ngpa->gpa->hpa)
94 addresses (gpa->hva); note that two gpas may alias to the same hva, but not
108 - writes to control registers (especially cr3)
109 - invlpg/invlpga instruction execution
110 - access to missing or protected translations
114 - changes in the gpa->hpa translation (either through gpa->hva changes or
115 through hva->hpa changes)
116 - memory pressure (the shrinker)
121 The principal data structure is the shadow page, 'struct kvm_mmu_page'. A
122 shadow page contains 512 sptes, which can be either leaf or nonleaf sptes. A
123 shadow page may contain a mix of leaf and nonleaf sptes.
129 one paging structure entry. These are always the lowest level of the
130 translation stack, with optional higher level translations left to NPT/EPT.
133 The following table shows translations encoded by leaf ptes, with higher-level
136 Non-nested guests::
138 nonpaging: gpa->hpa
139 paging: gva->gpa->hpa
140 paging, tdp: (gva->)gpa->hpa
144 non-tdp: ngva->gpa->hpa (*)
145 tdp: (ngva->)ngpa->gpa->hpa
147 (*) the guest hypervisor will encode the ngva->gpa translation into its page
151 role.level:
152 The level in the shadow paging hierarchy that this shadow page belongs to.
155 If set, leaf sptes reachable from this page are for a linear range.
157 host pages, and gpa->hpa translations when NPT or EPT is active.
159 by role.level (2MB for first level, 1GB for second level, 0.5TB for third
160 level, 256TB for fourth level)
161 If clear, this page corresponds to a guest page table denoted by the gfn
164 When role.gpte_is_8_bytes=0, the guest uses 32-bit gptes while the host uses 64-bit
165 sptes. That means a guest page table contains more ptes than the host,
166 so multiple shadow pages are needed to shadow one guest page.
167 For first-level shadow pages, role.quadrant can be 0 or 1 and denotes the
168 first or second 512-gpte block in the guest page table. For second-level
169 page tables, each 32-bit gpte is converted to two 64-bit sptes
170 (since each first-level guest page is shadowed by two first-level
177 The page is invalid and should not be used. It is a root page that is
181 Reflects the size of the guest PTE for which the page is valid, i.e. '1'
182 if 64-bit gptes are in use, '0' if 32-bit gptes are in use.
184 Contains the value of efer.nxe for which the page is valid.
186 Contains the value of cr0.wp for which the page is valid.
188 Contains the value of cr4.smep && !cr0.wp for which the page is valid
192 Contains the value of cr4.smap && !cr0.wp for which the page is valid
196 This is a virtual flag to denote a shadowed nested EPT page. ept_sp
199 Is 1 if the page is valid in system management mode. This field
201 shadow page; it is also used to go back from a struct kvm_mmu_page
206 bits before Haswell; shadow EPT page tables also cannot use A/D bits
209 Either the guest page table containing the translations shadowed by this
210 page, or the base page frame for linear translations. See role.direct.
212 A pageful of 64-bit sptes containing the translations for this page.
214 The page pointed to by spt will have its page->private pointing back
215 at the shadow page structure.
216 sptes in spt point either at guest pages, or at lower-level shadow pages.
217 Specifically, if sp1 and sp2 are shadow pages, then sp1->spt[n] may point
218 at __pa(sp2->spt). sp2 will point back at sp1 through parent_pte.
219 The spt array forms a DAG structure with the shadow page as a node, and
228 pdptrs) are now pointing at the page. While this counter is nonzero, the
229 page cannot be destroyed. See role.invalid.
231 The reverse mapping for the pte/ptes pointing at this page's spt. If
232 parent_ptes bit 0 is zero, only one spte points at this page and
234 sptes pointing at this page and (parent_ptes & ~0x1) points at a data
237 If true, then the translations in this page may not match the guest's
243 How many sptes in the page point at pages that are unsync (or have
248 pages reachable from a given page.
250 Only present on 32-bit hosts, where a 64-bit spte cannot be written
252 to detect in-progress updates and retry them until the writer has
255 A guest may write to a page table many times, causing a lot of
256 emulations if the page needs to be write-protected (see "Synchronized
259 possible for non-leafs. This field counts the number of emulations
260 since the last time the page table was actually used; if emulation
261 is triggered too frequently on this page, KVM will unmap the page
267 The mmu maintains a reverse mapping whereby all ptes mapping a page can be
268 reached given its gfn. This is used, for example, when swapping out a page.
273 The guest uses two events to synchronize its tlb and page tables: tlb flushes
274 and page invalidations (invlpg).
277 guest's cr3. This is expensive, so we keep all guest page tables write
280 A special case is when a guest page table is reachable from the current
283 protection from the guest page, and allowing the guest to modify it freely.
286 or when the a guest page is no longer used as a page table and is used for
296 - guest page fault (or npt page fault, or ept violation)
298 This is the most complicated event. The cause of a page fault can be:
300 - a true guest fault (the guest translation won't allow the access) (*)
301 - access to a missing translation
302 - access to a protected translation
303 - when logging dirty pages, memory is write protected
304 - synchronized shadow pages are write protected (*)
305 - access to untranslatable memory (mmio)
309 Handling a page fault is performed as follows:
311 - if the RSV bit of the error code is set, the page fault is caused by guest
314 - walk shadow page table
315 - check for valid generation number in the spte (see "Fast invalidation of
317 - cache the information to vcpu->arch.mmio_gva, vcpu->arch.mmio_access and
318 vcpu->arch.mmio_gfn, and call the emulator
320 - If both P bit and R/W bit of error code are set, this could possibly
321 be handled as a "fast page fault" (fixed without taking the MMU lock). See
324 - if needed, walk the guest page tables to determine the guest translation
325 (gva->gpa or ngpa->gpa)
327 - if permissions are insufficient, reflect the fault back to the guest
329 - determine the host page
331 - if this is an mmio request, there is no host page; cache the info to
332 vcpu->arch.mmio_gva, vcpu->arch.mmio_access and vcpu->arch.mmio_gfn
334 - walk the shadow page table to find the spte for the translation,
335 instantiating missing intermediate page tables as necessary
337 - If this is an mmio request, cache the mmio info to the spte and set some
340 - try to unsynchronize the page
342 - if successful, we can let the guest continue and modify the gpte
344 - emulate the instruction
346 - if failed, unshadow the page and let the guest continue
348 - update any translations that were modified by the instruction
352 - walk the shadow page hierarchy and drop affected translations
353 - try to reinstantiate the indicated translation in the hope that the
358 - mov to cr3
360 - look up new shadow roots
361 - synchronize newly reachable shadow pages
363 - mov to cr0/cr4/efer
365 - set up mmu context for new paging mode
366 - look up new shadow roots
367 - synchronize newly reachable shadow pages
371 - mmu notifier called with updated hva
372 - look up affected sptes through reverse map
373 - drop (or update) translations
378 If tdp is not enabled, the host must keep cr0.wp=1 so page write protection
387 - kernel write fault: spte.u=0, spte.w=1 (allows full kernel access,
389 - read fault: spte.u=1, spte.w=0 (allows full read access, disallows kernel
396 - if CR4.SMEP is enabled: since we've turned the page into a kernel page,
401 - if CR4.SMAP is disabled: since the page has been changed to a kernel
402 page, it can not be reused when CR4.SMAP is enabled. We set
403 CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note,
407 To prevent an spte that was converted into a kernel page with cr0.wp=0
409 the value of cr0.wp part of the page role. This means that an spte created
410 with one value of cr0.wp cannot be used when cr0.wp has a different value -
411 it will simply be missed by the shadow page lookup code. A similar issue
414 is also made a part of the page role.
420 Supported page sizes include 4k, 2M, 4M, and 1G. 4M pages are treated as
426 - the spte must point to a large host page
427 - the guest pte must be a large pte of at least equivalent size (if tdp is
429 - if the spte will be writeable, the large page frame may not overlap any
430 write-protected pages
431 - the guest page must be wholly contained by a single memory slot
433 To check the last two conditions, the mmu maintains a ->disallow_lpage set of
434 arrays for each memory slot and large page size. Every write protected page
437 artificially inflated ->disallow_lpages so they can never be instantiated.
450 kvm_memslots(kvm)->generation, and increased whenever guest memory info
455 number, it will ignore the cached MMIO information and handle the page
458 Since only 18 bits are used to store generation-number on mmio spte, all
464 out-of-date information, but with an up-to-date generation number.
467 returns; thus, bit 63 of kvm_memslots(kvm)->generation set to 1 only during a
470 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
473 spte while an update is in-progress, the next access to the spte will always be
475 miss due to the in-progress flag diverging, while an access after the update
482 - NPT presentation from KVM Forum 2008
483 https://www.linux-kvm.org/images/c/c8/KvmForum2008%24kdf2008_21.pdf