Lines Matching +full:saw +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
21 reg = <0xfa00000 0x200000>;
22 no-map;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 reg = <0>;
34 enable-method = "qcom,kpss-acc-v2";
35 next-level-cache = <&L2>;
37 qcom,saw = <&saw0>;
38 cpu-idle-states = <&CPU_SPC>;
44 reg = <1>;
45 enable-method = "qcom,kpss-acc-v2";
46 next-level-cache = <&L2>;
48 qcom,saw = <&saw1>;
49 cpu-idle-states = <&CPU_SPC>;
55 reg = <2>;
56 enable-method = "qcom,kpss-acc-v2";
57 next-level-cache = <&L2>;
59 qcom,saw = <&saw2>;
60 cpu-idle-states = <&CPU_SPC>;
66 reg = <3>;
67 enable-method = "qcom,kpss-acc-v2";
68 next-level-cache = <&L2>;
70 qcom,saw = <&saw3>;
71 cpu-idle-states = <&CPU_SPC>;
74 L2: l2-cache {
75 compatible = "qcom,arch-cache";
76 cache-level = <2>;
77 qcom,saw = <&saw_l2>;
80 idle-states {
82 compatible = "qcom,idle-state-spc",
83 "arm,idle-state";
84 entry-latency-us = <150>;
85 exit-latency-us = <200>;
86 min-residency-us = <2000>;
93 reg = <0x0 0x0>;
100 clock-names = "core", "bus", "iface";
104 thermal-zones {
105 cpu-thermal0 {
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
109 thermal-sensors = <&tsens 5>;
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
129 thermal-sensors = <&tsens 6>;
145 cpu-thermal2 {
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
149 thermal-sensors = <&tsens 7>;
165 cpu-thermal3 {
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
169 thermal-sensors = <&tsens 8>;
186 cpu-pmu {
187 compatible = "qcom,krait-pmu";
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <19200000>;
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <32768>;
206 compatible = "arm,armv7-timer";
211 clock-frequency = <19200000>;
217 qcom,rpm-msg-ram = <&rpm_msg_ram>;
218 memory-region = <&smem_mem>;
224 #address-cells = <1>;
225 #size-cells = <1>;
227 compatible = "simple-bus";
229 intc: interrupt-controller@f9000000 {
230 compatible = "qcom,msm-qgic2";
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 reg = <0xf9000000 0x1000>,
239 reg = <0xf9011000 0x1000>;
243 #address-cells = <1>;
244 #size-cells = <1>;
246 reg = <0xfc4bc000 0x1000>;
248 reg = <0xd0 0x18>;
251 reg = <0x440 0x10>;
255 tsens: thermal-sensor@fc4a8000 {
256 compatible = "qcom,msm8974-tsens";
257 reg = <0xfc4a9000 0x1000>, /* TM */
259 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
260 nvmem-cell-names = "calib", "calib_backup";
262 #thermal-sensor-cells = <1>;
265 #address-cells = <1>;
266 #size-cells = <1>;
268 compatible = "arm,armv7-timer-mem";
269 reg = <0xf9020000 0x1000>;
270 clock-frequency = <19200000>;
273 frame-number = <0>;
276 reg = <0xf9021000 0x1000>,
281 frame-number = <1>;
283 reg = <0xf9023000 0x1000>;
288 frame-number = <2>;
290 reg = <0xf9024000 0x1000>;
295 frame-number = <3>;
297 reg = <0xf9025000 0x1000>;
302 frame-number = <4>;
304 reg = <0xf9026000 0x1000>;
309 frame-number = <5>;
311 reg = <0xf9027000 0x1000>;
316 frame-number = <6>;
318 reg = <0xf9028000 0x1000>;
323 saw0: power-controller@f9089000 {
324 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
325 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
328 saw1: power-controller@f9099000 {
329 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
330 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
333 saw2: power-controller@f90a9000 {
334 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
335 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
338 saw3: power-controller@f90b9000 {
339 compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
340 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
343 saw_l2: power-controller@f9012000 {
345 reg = <0xf9012000 0x1000>;
349 acc0: clock-controller@f9088000 {
350 compatible = "qcom,kpss-acc-v2";
351 reg = <0xf9088000 0x1000>,
355 acc1: clock-controller@f9098000 {
356 compatible = "qcom,kpss-acc-v2";
357 reg = <0xf9098000 0x1000>,
361 acc2: clock-controller@f90a8000 {
362 compatible = "qcom,kpss-acc-v2";
363 reg = <0xf90a8000 0x1000>,
367 acc3: clock-controller@f90b8000 {
368 compatible = "qcom,kpss-acc-v2";
369 reg = <0xf90b8000 0x1000>,
375 reg = <0xfc4ab000 0x4>;
378 gcc: clock-controller@fc400000 {
379 compatible = "qcom,gcc-apq8084";
380 #clock-cells = <1>;
381 #reset-cells = <1>;
382 #power-domain-cells = <1>;
383 reg = <0xfc400000 0x4000>;
388 reg = <0xfd484000 0x2000>;
392 compatible = "qcom,tcsr-mutex";
394 #hwlock-cells = <1>;
398 compatible = "qcom,rpm-msg-ram";
399 reg = <0xfc428000 0x4000>;
403 compatible = "qcom,apq8084-pinctrl";
404 reg = <0xfd510000 0x4000>;
405 gpio-controller;
406 gpio-ranges = <&tlmm 0 0 147>;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
414 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
415 reg = <0xf995e000 0x1000>;
418 clock-names = "core", "iface";
423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
425 reg-names = "hc_mem", "core_mem";
427 interrupt-names = "hc_irq", "pwr_irq";
431 clock-names = "core", "iface", "xo";
436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
438 reg-names = "hc_mem", "core_mem";
440 interrupt-names = "hc_irq", "pwr_irq";
444 clock-names = "core", "iface", "xo";
449 compatible = "qcom,spmi-pmic-arb";
450 reg-names = "core", "intr", "cnfg";
451 reg = <0xfc4cf000 0x1000>,
454 interrupt-names = "periph_irq";
458 #address-cells = <2>;
459 #size-cells = <0>;
460 interrupt-controller;
461 #interrupt-cells = <4>;
471 qcom,smd-edge = <15>;
474 compatible = "qcom,rpm-apq8084";
475 qcom,smd-channels = "rpm_requests";
477 pma8084-regulators {
478 compatible = "qcom,rpm-pma8084-regulators";