Lines Matching +full:secondary +full:- +full:boot +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
50 * - KVM exposes its own view of the feature registers to guest operating
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
115 * capabilities based on the boot time active CPUs. This
131 /* file-wide pr_fmt adds "CPU features: " prefix */ in dump_cpu_features()
278 * Page size not being supported at Stage-2 is not fatal. You
283 * advertises a given granule size at Stage-2 (value 2) on some
284 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
296 * We already refuse to boot CPUs that don't support our configured
300 * along with it and treat them as non-strict.
361 * Linux can handle differing I-cache policies. Userspace JITs will
363 * If we have differing I-cache policies, report it as the weakest - VIPT.
537 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
563 .reg = &(struct arm64_ftr_reg){ \
570 struct arm64_ftr_reg *reg; member
632 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; in search_cmp_ftr_reg()
636 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
641 * returns - Upon success, matching ftr_reg entry for id.
642 * - NULL on failure. It is upto the caller to decide
655 return ret->reg; in get_arm64_ftr_reg_nowarn()
660 * get_arm64_ftr_reg - Looks up a feature register entry using
663 * returns - Upon success, matching ftr_reg entry for id.
664 * - NULL on failure but with an WARN_ON().
668 struct arm64_ftr_reg *reg; in get_arm64_ftr_reg() local
670 reg = get_arm64_ftr_reg_nowarn(sys_id); in get_arm64_ftr_reg()
673 * Requesting a non-existent register search is an error. Warn in get_arm64_ftr_reg()
676 WARN_ON(!reg); in get_arm64_ftr_reg()
677 return reg; in get_arm64_ftr_reg()
680 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, in arm64_ftr_set_value() argument
685 reg &= ~mask; in arm64_ftr_set_value()
686 reg |= (ftr_val << ftrp->shift) & mask; in arm64_ftr_set_value()
687 return reg; in arm64_ftr_set_value()
695 switch (ftrp->type) { in arm64_ftr_safe_value()
697 ret = ftrp->safe_val; in arm64_ftr_safe_value()
721 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; in sort_ftr_regs()
722 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; in sort_ftr_regs()
729 for (; ftr_bits->width != 0; ftr_bits++, j++) { in sort_ftr_regs()
730 unsigned int width = ftr_reg->ftr_bits[j].width; in sort_ftr_regs()
731 unsigned int shift = ftr_reg->ftr_bits[j].shift; in sort_ftr_regs()
736 ftr_reg->name, shift); in sort_ftr_regs()
745 prev_shift = ftr_reg->ftr_bits[j - 1].shift; in sort_ftr_regs()
748 ftr_reg->name, shift); in sort_ftr_regs()
762 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); in sort_ftr_regs()
767 * Initialise the CPU feature register from Boot CPU values.
770 * RES0 for the system-wide value, and must strictly match.
780 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); in init_cpu_ftr_reg() local
782 if (!reg) in init_cpu_ftr_reg()
785 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in init_cpu_ftr_reg()
792 if (!ftrp->strict) in init_cpu_ftr_reg()
794 if (ftrp->visible) in init_cpu_ftr_reg()
797 reg->user_val = arm64_ftr_set_value(ftrp, in init_cpu_ftr_reg()
798 reg->user_val, in init_cpu_ftr_reg()
799 ftrp->safe_val); in init_cpu_ftr_reg()
804 reg->sys_val = val; in init_cpu_ftr_reg()
805 reg->strict_mask = strict_mask; in init_cpu_ftr_reg()
806 reg->user_mask = user_mask; in init_cpu_ftr_reg()
815 for (; caps->matches; caps++) { in init_cpu_hwcaps_indirect_list_from_array()
816 if (WARN(caps->capability >= ARM64_NCAPS, in init_cpu_hwcaps_indirect_list_from_array()
817 "Invalid capability %d\n", caps->capability)) in init_cpu_hwcaps_indirect_list_from_array()
819 if (WARN(cpu_hwcaps_ptrs[caps->capability], in init_cpu_hwcaps_indirect_list_from_array()
821 caps->capability)) in init_cpu_hwcaps_indirect_list_from_array()
823 cpu_hwcaps_ptrs[caps->capability] = caps; in init_cpu_hwcaps_indirect_list_from_array()
840 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); in init_cpu_features()
841 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); in init_cpu_features()
842 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); in init_cpu_features()
843 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); in init_cpu_features()
844 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); in init_cpu_features()
845 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); in init_cpu_features()
846 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); in init_cpu_features()
847 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); in init_cpu_features()
848 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); in init_cpu_features()
849 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); in init_cpu_features()
850 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); in init_cpu_features()
851 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); in init_cpu_features()
852 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); in init_cpu_features()
853 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); in init_cpu_features()
855 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { in init_cpu_features()
856 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); in init_cpu_features()
857 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); in init_cpu_features()
858 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); in init_cpu_features()
859 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); in init_cpu_features()
860 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); in init_cpu_features()
861 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); in init_cpu_features()
862 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); in init_cpu_features()
863 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); in init_cpu_features()
864 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); in init_cpu_features()
865 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); in init_cpu_features()
866 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); in init_cpu_features()
867 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); in init_cpu_features()
868 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); in init_cpu_features()
869 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); in init_cpu_features()
870 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); in init_cpu_features()
871 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); in init_cpu_features()
872 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); in init_cpu_features()
873 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); in init_cpu_features()
874 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); in init_cpu_features()
875 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); in init_cpu_features()
876 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); in init_cpu_features()
879 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { in init_cpu_features()
880 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); in init_cpu_features()
886 * before we handle the boot CPU below. in init_cpu_features()
891 * Detect and enable early CPU capabilities based on the boot CPU, in init_cpu_features()
897 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) in update_cpu_ftr_reg() argument
901 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in update_cpu_ftr_reg()
902 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); in update_cpu_ftr_reg()
909 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); in update_cpu_ftr_reg()
914 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) in check_update_ftr_reg() argument
922 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) in check_update_ftr_reg()
924 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", in check_update_ftr_reg()
925 regp->name, boot, cpu, val); in check_update_ftr_reg()
937 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { in relax_cpu_ftr_reg()
938 if (ftrp->shift == field) { in relax_cpu_ftr_reg()
939 regp->strict_mask &= ~arm64_ftr_mask(ftrp); in relax_cpu_ftr_reg()
945 WARN_ON(!ftrp->width); in relax_cpu_ftr_reg()
949 struct cpuinfo_arm64 *boot) in update_32bit_cpu_features() argument
964 * EL1-dependent register fields to avoid spurious sanity check fails. in update_32bit_cpu_features()
976 info->reg_id_dfr0, boot->reg_id_dfr0); in update_32bit_cpu_features()
978 info->reg_id_dfr1, boot->reg_id_dfr1); in update_32bit_cpu_features()
980 info->reg_id_isar0, boot->reg_id_isar0); in update_32bit_cpu_features()
982 info->reg_id_isar1, boot->reg_id_isar1); in update_32bit_cpu_features()
984 info->reg_id_isar2, boot->reg_id_isar2); in update_32bit_cpu_features()
986 info->reg_id_isar3, boot->reg_id_isar3); in update_32bit_cpu_features()
988 info->reg_id_isar4, boot->reg_id_isar4); in update_32bit_cpu_features()
990 info->reg_id_isar5, boot->reg_id_isar5); in update_32bit_cpu_features()
992 info->reg_id_isar6, boot->reg_id_isar6); in update_32bit_cpu_features()
1000 info->reg_id_mmfr0, boot->reg_id_mmfr0); in update_32bit_cpu_features()
1002 info->reg_id_mmfr1, boot->reg_id_mmfr1); in update_32bit_cpu_features()
1004 info->reg_id_mmfr2, boot->reg_id_mmfr2); in update_32bit_cpu_features()
1006 info->reg_id_mmfr3, boot->reg_id_mmfr3); in update_32bit_cpu_features()
1008 info->reg_id_mmfr4, boot->reg_id_mmfr4); in update_32bit_cpu_features()
1010 info->reg_id_mmfr5, boot->reg_id_mmfr5); in update_32bit_cpu_features()
1012 info->reg_id_pfr0, boot->reg_id_pfr0); in update_32bit_cpu_features()
1014 info->reg_id_pfr1, boot->reg_id_pfr1); in update_32bit_cpu_features()
1016 info->reg_id_pfr2, boot->reg_id_pfr2); in update_32bit_cpu_features()
1018 info->reg_mvfr0, boot->reg_mvfr0); in update_32bit_cpu_features()
1020 info->reg_mvfr1, boot->reg_mvfr1); in update_32bit_cpu_features()
1022 info->reg_mvfr2, boot->reg_mvfr2); in update_32bit_cpu_features()
1029 * non-boot CPU. Also performs SANITY checks to make sure that there
1030 * aren't any insane variations from that of the boot CPU.
1034 struct cpuinfo_arm64 *boot) in update_cpu_features() argument
1039 * The kernel can handle differing I-cache policies, but otherwise in update_cpu_features()
1044 info->reg_ctr, boot->reg_ctr); in update_cpu_features()
1052 info->reg_dczid, boot->reg_dczid); in update_cpu_features()
1056 info->reg_cntfrq, boot->reg_cntfrq); in update_cpu_features()
1059 * The kernel uses self-hosted debug features and expects CPUs to in update_cpu_features()
1065 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); in update_cpu_features()
1067 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); in update_cpu_features()
1069 * Even in big.LITTLE, processors should be identical instruction-set in update_cpu_features()
1073 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); in update_cpu_features()
1075 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); in update_cpu_features()
1077 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); in update_cpu_features()
1085 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); in update_cpu_features()
1087 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); in update_cpu_features()
1089 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); in update_cpu_features()
1092 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); in update_cpu_features()
1094 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); in update_cpu_features()
1097 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); in update_cpu_features()
1099 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { in update_cpu_features()
1101 info->reg_zcr, boot->reg_zcr); in update_cpu_features()
1113 taint |= update_32bit_cpu_features(cpu, info, boot); in update_cpu_features()
1131 return regp->sys_val; in read_sanitised_ftr_reg()
1139 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1189 #include <linux/irqchip/arm-gic-v3.h>
1192 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) in feature_matches() argument
1194 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); in feature_matches()
1196 return val >= entry->min_field_value; in feature_matches()
1206 val = read_sanitised_ftr_reg(entry->sys_reg); in has_cpuid_feature()
1208 val = __read_sysreg_by_encoding(entry->sys_reg); in has_cpuid_feature()
1223 entry->desc); in has_useable_gicv3_cpuif()
1288 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP in has_useable_cnp()
1299 * This check is triggered during the early boot before the cpufeature
1300 * is initialised. Checking the status on the local CPU allows the boot
1301 * CPU to detect the need for non-global mappings and thus avoiding a
1302 * pagetable re-write after all the CPUs are booted. This check will be
1304 * state once the SMP CPUs are up and thus make the switch to non-global
1377 * ThunderX leads to apparent I-cache corruption of kernel text, which in unmap_kernel_at_el0()
1382 __kpti_forced = -1; in unmap_kernel_at_el0()
1395 __kpti_forced = -1; in unmap_kernel_at_el0()
1430 * We don't need to rewrite the page-tables if either we've done in kpti_install_ng_mappings()
1463 __kpti_forced = enabled ? 1 : -1; in parse_kpti()
1510 * DBM is a non-conflicting feature. i.e, the kernel can safely in has_hw_dbm()
1520 * This is safe as all CPUs (including secondary CPUs - due to the in has_hw_dbm()
1521 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) in has_hw_dbm()
1574 * The AMU extension is a non-conflicting feature: the kernel can in has_amu()
1581 * including secondary and hotplugged, marking this feature as in has_amu()
1603 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to in cpu_copy_el2regs()
1649 * The ptr-auth feature levels are not intercompatible with lower in has_address_auth_cpucap()
1650 * levels. Hence we must match ptr-auth feature level of the secondary in has_address_auth_cpucap()
1651 * CPUs with that of the boot CPU. The level of boot cpu is fetched in has_address_auth_cpucap()
1653 * the secondary CPUs. in has_address_auth_cpucap()
1655 * boot CPU as a mismatched secondary CPU is parked before it gets in has_address_auth_cpucap()
1658 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap()
1659 entry->field_pos, entry->sign); in has_address_auth_cpucap()
1661 return boot_val >= entry->min_field_value; in has_address_auth_cpucap()
1662 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ in has_address_auth_cpucap()
1663 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap()
1664 entry->field_pos, entry->sign); in has_address_auth_cpucap()
1711 * Use of X16/X17 for tail-calls and trampolines that jump to in bti_enable()
1729 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) in cpu_enable_mte()
1746 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); in cpucap_late_cpu_optional()
1752 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); in cpucap_late_cpu_permitted()
1758 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); in cpucap_panic_on_conflict()
1835 .desc = "32-bit EL0 Support",
1846 .desc = "32-bit EL1 Support",
1957 .desc = "Stage-2 Force Write-Back",
2174 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ argument
2176 .sys_reg = reg, \
2187 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ argument
2190 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2302 * check is future proof, by making sure value is non-zero. in compat_has_neon()
2336 switch (cap->hwcap_type) { in cap_set_elf_hwcap()
2338 cpu_set_feature(cap->hwcap); in cap_set_elf_hwcap()
2342 compat_elf_hwcap |= (u32)cap->hwcap; in cap_set_elf_hwcap()
2345 compat_elf_hwcap2 |= (u32)cap->hwcap; in cap_set_elf_hwcap()
2359 switch (cap->hwcap_type) { in cpus_have_elf_hwcap()
2361 rc = cpu_have_feature(cap->hwcap); in cpus_have_elf_hwcap()
2365 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
2368 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
2383 for (; hwcaps->matches; hwcaps++) in setup_elf_hwcaps()
2384 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) in setup_elf_hwcaps()
2396 if (!caps || !(caps->type & scope_mask) || in update_cpu_capabilities()
2397 cpus_have_cap(caps->capability) || in update_cpu_capabilities()
2398 !caps->matches(caps, cpucap_default_scope(caps))) in update_cpu_capabilities()
2401 if (caps->desc) in update_cpu_capabilities()
2402 pr_info("detected: %s\n", caps->desc); in update_cpu_capabilities()
2403 cpus_set_cap(caps->capability); in update_cpu_capabilities()
2405 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) in update_cpu_capabilities()
2406 set_bit(caps->capability, boot_capabilities); in update_cpu_capabilities()
2425 if (!(cap->type & non_boot_scope)) in cpu_enable_non_boot_scope_capabilities()
2428 if (cap->cpu_enable) in cpu_enable_non_boot_scope_capabilities()
2429 cap->cpu_enable(cap); in cpu_enable_non_boot_scope_capabilities()
2451 if (!caps || !(caps->type & scope_mask)) in enable_cpu_capabilities()
2453 num = caps->capability; in enable_cpu_capabilities()
2460 if (boot_scope && caps->cpu_enable) in enable_cpu_capabilities()
2463 * before any secondary CPU boots. Thus, each secondary in enable_cpu_capabilities()
2466 * the boot CPU, for which the capability must be in enable_cpu_capabilities()
2470 caps->cpu_enable(caps); in enable_cpu_capabilities()
2474 * For all non-boot scope capabilities, use stop_machine() in enable_cpu_capabilities()
2499 if (!caps || !(caps->type & scope_mask)) in verify_local_cpu_caps()
2502 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); in verify_local_cpu_caps()
2503 system_has_cap = cpus_have_cap(caps->capability); in verify_local_cpu_caps()
2518 if (caps->cpu_enable) in verify_local_cpu_caps()
2519 caps->cpu_enable(caps); in verify_local_cpu_caps()
2532 smp_processor_id(), caps->capability, in verify_local_cpu_caps()
2533 caps->desc, system_has_cap, cpu_has_cap); in verify_local_cpu_caps()
2543 * Check for CPU features that are used in early boot
2544 * based on the Boot CPU value.
2557 for (; caps->matches; caps++) in verify_local_elf_hwcaps()
2558 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { in verify_local_elf_hwcaps()
2560 smp_processor_id(), caps->desc); in verify_local_elf_hwcaps()
2615 * The capabilities were decided based on the available CPUs at the boot time.
2626 * on all secondary CPUs. in verify_local_cpu_capabilities()
2645 * All secondary CPUs should conform to the early CPU features in check_local_cpu_capabilities()
2646 * in use by the kernel based on boot CPU. in check_local_cpu_capabilities()
2676 return cap->matches(cap, SCOPE_LOCAL_CPU); in this_cpu_has_cap()
2684 * - The system wide safe registers are set with all the SMP CPUs and,
2685 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2694 return cap->matches(cap, SCOPE_SYSTEM); in __system_matches_cap()
2731 * We have finalised the system-wide safe feature in setup_system_capabilities()
2783 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2784 * See Table C5-6 System instruction encodings for System register accesses,
2797 * With CRm == 0, reg should be one of :
2814 return -EINVAL; in emulate_id_reg()
2825 return -EINVAL; in emulate_sys_reg()