51 	u64 addr, data = 0;  in raw_pci_read()
59 		mode = 0;  in raw_pci_read()
68 	if (result != 0)  in raw_pci_read()
72 	return 0;  in raw_pci_read()
86 		mode = 0;  in raw_pci_write()
94 	if (result != 0)  in raw_pci_write()
96 	return 0;  in raw_pci_write()
129 	if (phys_base == 0)  in new_space()
130 		return 0;	/* legacy I/O port space */  in new_space()
132 	mmio_base = (u64) ioremap(phys_base, 0);  in new_space()
133 	for (i = 0; i < num_io_spaces; i++)  in new_space()
141 		return ~0;  in new_space()
158 	unsigned int sparse = 0, space_nr, len;  in add_io_space()
171 	if (space_nr == ~0)  in add_io_space()
183 	 * The SDM guarantees the legacy 0-64K space is sparse, but if the  in add_io_space()
187 	if (space_nr == 0)  in add_io_space()
207 	return 0;  in add_io_space()
223  *     IO port [0xCF8-0xCFF] is consumed by the host bridge itself
226  * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
231 		res->start == 0xCF8 && res->end == 0xCFF;  in resource_is_pcicfg_ioport()
243 	if (status > 0) {  in pci_acpi_root_prepare_resources()
323 	return 0;  in pcibios_root_bridge_prepare()
333 	for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {  in pcibios_fixup_device_resources()
397 	if (ret < 0)  in pcibios_enable_device()
402 	return 0;  in pcibios_enable_device()
418  * megabyte of bus address space for @bus or is simply 0 on platforms whose
470 	return 0;  in pci_mmap_legacy_page_range()
554 	if (status != 0) {  in set_pci_dfl_cacheline_size()
562 	if (status != 0) {  in set_pci_dfl_cacheline_size()
573 	return 0;  in pcibios_init()