Lines Matching +full:0 +full:x04000
20 #define MIPS_GIC_SHARED_OFS 0x00000
21 #define MIPS_GIC_SHARED_SZ 0x08000
22 #define MIPS_GIC_LOCAL_OFS 0x08000
23 #define MIPS_GIC_LOCAL_SZ 0x04000
24 #define MIPS_GIC_REDIR_OFS 0x0c000
25 #define MIPS_GIC_REDIR_SZ 0x04000
26 #define MIPS_GIC_USER_OFS 0x10000
27 #define MIPS_GIC_USER_SZ 0x10000
105 return val & 0x1; \
164 GIC_ACCESSOR_RW(32, 0x000, config)
168 #define GIC_CONFIG_PVPS GENMASK(6, 0)
171 GIC_ACCESSOR_RW(64, 0x010, counter)
172 GIC_ACCESSOR_RW(32, 0x010, counter_32l)
173 GIC_ACCESSOR_RW(32, 0x014, counter_32h)
176 GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
177 #define GIC_POL_ACTIVE_LOW 0 /* when level triggered */
179 #define GIC_POL_FALLING_EDGE 0 /* when single-edge triggered */
183 GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
184 #define GIC_TRIG_LEVEL 0
188 GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
189 #define GIC_DUAL_SINGLE 0 /* when edge-triggered */
193 GIC_ACCESSOR_RW(32, 0x280, wedge)
195 #define GIC_WEDGE_INTR GENMASK(7, 0)
198 GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)
201 GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)
204 GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)
207 GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)
210 GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
213 #define GIC_MAP_PIN_MAP GENMASK(5, 0)
216 GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
219 GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
224 #define GIC_VX_CTL_EIC BIT(0)
227 GIC_VX_ACCESSOR_RO(32, 0x004, pend)
230 GIC_VX_ACCESSOR_RO(32, 0x008, mask)
233 GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
236 GIC_VX_ACCESSOR_RW(32, 0x010, smask)
239 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
242 GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
245 GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
248 GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
251 GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
254 GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
256 /* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
257 GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
260 GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
263 GIC_VX_ACCESSOR_RW(32, 0x080, other)
264 #define GIC_VX_OTHER_VPNUM GENMASK(5, 0)
267 GIC_VX_ACCESSOR_RO(32, 0x088, ident)
268 #define GIC_VX_IDENT_VPNUM GENMASK(5, 0)
271 GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)
274 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)
282 * @GIC_LOCAL_INT_SWINT0: Software interrupt 0
346 * Determine the virq number to use for the coprocessor 0 count/compare