Lines Matching +full:0 +full:x40c00000
45 * Coprocessor 0 register names
47 #define CP0_INDEX $0
106 #define CP0_IBASE $0
115 * Coprocessor 0 Set 1 register names
122 * Coprocessor 0 Set 2 register names
127 * Coprocessor 0 Set 3 register names
138 #define ENTRYLO_G (_ULCAST_(1) << 0)
158 #define MIPS_GLOBALNUMBER_VP_SHF 0
159 #define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
161 #define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
163 #define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
172 #define PM_1K 0x00000000
173 #define PM_4K 0x00001800
174 #define PM_16K 0x00007800
175 #define PM_64K 0x0001f800
176 #define PM_256K 0x0007f800
180 #define PM_4K 0x00000000
181 #define PM_8K 0x00002000
182 #define PM_16K 0x00006000
183 #define PM_32K 0x0000e000
184 #define PM_64K 0x0001e000
185 #define PM_128K 0x0003e000
186 #define PM_256K 0x0007e000
187 #define PM_512K 0x000fe000
188 #define PM_1M 0x001fe000
189 #define PM_2M 0x003fe000
190 #define PM_4M 0x007fe000
191 #define PM_8M 0x00ffe000
192 #define PM_16M 0x01ffe000
193 #define PM_32M 0x03ffe000
194 #define PM_64M 0x07ffe000
195 #define PM_256M 0x1fffe000
196 #define PM_1G 0x7fffe000
238 #define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
239 #define MIPSR6_WIRED_WIRED_SHIFT 0
240 #define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
266 #define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
267 #define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
296 #define ST0_IE 0x00000001
297 #define ST0_EXL 0x00000002
298 #define ST0_ERL 0x00000004
299 #define ST0_KSU 0x00000018
300 # define KSU_USER 0x00000010
301 # define KSU_SUPERVISOR 0x00000008
302 # define KSU_KERNEL 0x00000000
303 #define ST0_UX 0x00000020
304 #define ST0_SX 0x00000040
305 #define ST0_KX 0x00000080
306 #define ST0_DE 0x00010000
307 #define ST0_CE 0x00020000
314 #define ST0_CO 0x08000000
319 #define ST0_IEC 0x00000001
320 #define ST0_KUC 0x00000002
321 #define ST0_IEP 0x00000004
322 #define ST0_KUP 0x00000008
323 #define ST0_IEO 0x00000010
324 #define ST0_KUO 0x00000020
326 #define ST0_ISC 0x00010000
327 #define ST0_SWC 0x00020000
328 #define ST0_CM 0x00080000
340 #define ST0_MX 0x01000000
345 #define ST0_IM 0x0000ff00
362 #define STATUSB_IP8 0
363 #define STATUSF_IP8 (_ULCAST_(1) << 0)
378 #define ST0_CH 0x00040000
379 #define ST0_NMI 0x00080000
380 #define ST0_SR 0x00100000
381 #define ST0_TS 0x00200000
382 #define ST0_BEV 0x00400000
383 #define ST0_RE 0x02000000
384 #define ST0_FR 0x04000000
385 #define ST0_CU 0xf0000000
386 #define ST0_CU0 0x10000000
387 #define ST0_CU1 0x20000000
388 #define ST0_CU2 0x40000000
389 #define ST0_CU3 0x80000000
390 #define ST0_XX 0x80000000 /* MIPS IV naming */
400 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
410 * Bitfields and bit numbers in the coprocessor 0 cause register.
454 #define EXCCODE_INT 0 /* Interrupt pending */
488 * Bits in the coprocessor 0 config register.
491 #define CONF_CM_CACHABLE_NO_WA 0
592 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
594 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
623 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
632 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
660 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
661 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
662 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
683 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
703 #define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
741 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
752 #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
757 #define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
758 #define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
761 #define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
762 #define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
763 #define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
766 #define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
767 #define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
770 #define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
776 #define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
778 #define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
779 #define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
788 #define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
790 #define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
791 #define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
792 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
807 #define MIPS_MAAR_VL (_ULCAST_(1) << 0)
814 #define MIPS_MAARX_ADDR 0xF
818 #define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
821 #define MIPS_EBASE_CPUNUM_SHIFT 0
822 #define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
833 #define MIPS_LLADDR_LLB_SHIFT 0
845 #define MIPS_SEGCFG_C_SHIFT 0
854 #define MIPS_SEGCFG_UK _ULCAST_(0)
857 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
859 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
861 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
863 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
864 #define MIPS_PWFIELD_PTEI_SHIFT 0
865 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
868 #define MIPS_PWSIZE_PS_MASK 0x40000000
870 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
872 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
874 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
876 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
877 #define MIPS_PWSIZE_PTEW_SHIFT 0
878 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
881 #define MIPS_PWCTL_PWEN_MASK 0x80000000
883 #define MIPS_PWCTL_XK_MASK 0x10000000
885 #define MIPS_PWCTL_XS_MASK 0x08000000
887 #define MIPS_PWCTL_XU_MASK 0x04000000
889 #define MIPS_PWCTL_DPH_MASK 0x00000080
891 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
892 #define MIPS_PWCTL_PSN_SHIFT 0
893 #define MIPS_PWCTL_PSN_MASK 0x0000003f
905 #define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
925 #define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
928 #define MIPS_GCTL0_SFC1_SHIFT 0
936 #define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
946 #define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
948 #define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
957 #define MIPS_GCTL0EXT_MG_SHIFT 0
961 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
966 #define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
970 #define MIPS_GCTL1_ID_SHIFT 0
972 #define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
975 #define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
978 #define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
981 #define MIPS_GCTL1_ROOT_GUESTID 0
984 #define MIPS_CDMMBASE_SIZE_SHIFT 0
992 #define MIPS_HWR_CPUNUM 0 /* CPU number */
1013 #define TX39_CONF_ICS_MASK 0x00380000
1014 #define TX39_CONF_ICS_1KB 0x00000000
1015 #define TX39_CONF_ICS_2KB 0x00080000
1016 #define TX39_CONF_ICS_4KB 0x00100000
1017 #define TX39_CONF_ICS_8KB 0x00180000
1018 #define TX39_CONF_ICS_16KB 0x00200000
1021 #define TX39_CONF_DCS_MASK 0x00070000
1022 #define TX39_CONF_DCS_1KB 0x00000000
1023 #define TX39_CONF_DCS_2KB 0x00010000
1024 #define TX39_CONF_DCS_4KB 0x00020000
1025 #define TX39_CONF_DCS_8KB 0x00030000
1026 #define TX39_CONF_DCS_16KB 0x00040000
1028 #define TX39_CONF_CWFON 0x00004000
1029 #define TX39_CONF_WBON 0x00002000
1031 #define TX39_CONF_RF_MASK 0x00000c00
1032 #define TX39_CONF_DOZE 0x00000200
1033 #define TX39_CONF_HALT 0x00000100
1034 #define TX39_CONF_LOCK 0x00000080
1035 #define TX39_CONF_ICE 0x00000020
1036 #define TX39_CONF_DCE 0x00000010
1038 #define TX39_CONF_IRSIZE_MASK 0x0000000c
1039 #define TX39_CONF_DRSIZE_SHIFT 0
1040 #define TX39_CONF_DRSIZE_MASK 0x00000003
1074 #define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1076 #define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1084 #define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1085 #define CVMVMCONF_RMMUSIZEM1_S 0
1086 #define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1091 #define CP1_REVISION $0
1117 #define MIPS_FCCR_CONDX_S 0
1119 #define MIPS_FCCR_COND0_S 0
1148 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1169 * Bits 22:20 of the FPU Status Register will be read as 0,
1185 #define FPU_CSR_ALL_X 0x0003f000
1186 #define FPU_CSR_UNI_X 0x00020000
1187 #define FPU_CSR_INV_X 0x00010000
1188 #define FPU_CSR_DIV_X 0x00008000
1189 #define FPU_CSR_OVF_X 0x00004000
1190 #define FPU_CSR_UDF_X 0x00002000
1191 #define FPU_CSR_INE_X 0x00001000
1193 #define FPU_CSR_ALL_E 0x00000f80
1194 #define FPU_CSR_INV_E 0x00000800
1195 #define FPU_CSR_DIV_E 0x00000400
1196 #define FPU_CSR_OVF_E 0x00000200
1197 #define FPU_CSR_UDF_E 0x00000100
1198 #define FPU_CSR_INE_E 0x00000080
1200 #define FPU_CSR_ALL_S 0x0000007c
1201 #define FPU_CSR_INV_S 0x00000040
1202 #define FPU_CSR_DIV_S 0x00000020
1203 #define FPU_CSR_OVF_S 0x00000010
1204 #define FPU_CSR_UDF_S 0x00000008
1205 #define FPU_CSR_INE_S 0x00000004
1207 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1208 #define FPU_CSR_RM 0x00000003
1209 #define FPU_CSR_RN 0x0 /* nearest */
1210 #define FPU_CSR_RZ 0x1 /* towards zero */
1211 #define FPU_CSR_RU 0x2 /* towards +Infinity */
1212 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1222 #define get_isa16_mode(x) ((x) & 0x1)
1223 #define msk_isa16_mode(x) ((x) & ~0x1)
1224 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1226 #define get_isa16_mode(x) 0
1228 #define set_isa16_mode(x) do { } while(0)
1233 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1237 u16 opcode = (insn >> 10) & 0x7; in mm_insn_16bit()
1239 return (opcode >= 1 && opcode <= 3) ? 1 : 0; in mm_insn_16bit()
1252 ".hword ((" #_enc ") & 0xffff)\n\t"
1283 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1285 * "# di %0\n\t"
1286 * ".word (0x41606000 | (__rt << 16))"
1298 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1353 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1368 _ASM_INSN_IF_MIPS(0x42000004) in tlbinvf()
1369 _ASM_INSN32_IF_MM(0x0000537c) in tlbinvf()
1378 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1379 * disassembler these will look like an access to sel 0 or 1.
1385 "mfpc\t%0, %1" \
1395 "mtpc\t%0, %1" \
1398 } while (0)
1404 "mfps\t%0, %1" \
1414 "mtps\t%0, %1" \
1417 } while (0)
1426 if (sel == 0) \
1428 "mfc0\t%0, " #source "\n\t" \
1434 "mfc0\t%0, " #source ", " #sel "\n\t" \
1444 else if (sel == 0) \
1448 "dmfc0\t%0, " #source "\n\t" \
1455 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1475 if (sel == 0) \
1486 } while (0)
1492 else if (sel == 0) \
1506 } while (0)
1524 } while (0)
1532 "cfc0\t%0, " #source "\n\t" \
1542 } while (0)
1554 if (sel == 0) \
1560 "sll\t%L0, %L0, 0\n\t" \
1569 "sll\t%L0, %L0, 0\n\t" \
1591 else if (sel == 0) \
1614 } while (0)
1618 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1619 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1621 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1622 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1636 " mfhc0 %0, " #source ", %1 \n" \
1653 } while (0)
1655 #define read_c0_index() __read_32bit_c0_register($0, 0)
1656 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1658 #define read_c0_random() __read_32bit_c0_register($1, 0)
1659 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1661 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1662 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1664 #define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1665 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1667 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1668 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1670 #define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1671 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1673 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1674 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1678 #define read_c0_context() __read_ulong_c0_register($4, 0)
1679 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1693 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1694 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1699 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1700 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1702 #define read_c0_info() __read_32bit_c0_register($7, 0)
1704 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1705 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1707 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1708 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1713 #define read_c0_count() __read_32bit_c0_register($9, 0)
1714 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1716 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1717 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1728 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1729 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1734 #define read_c0_status() __read_32bit_c0_register($12, 0)
1736 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1744 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1745 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1747 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1748 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1750 #define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1754 #define read_c0_config() __read_32bit_c0_register($16, 0)
1762 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1771 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1772 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1783 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1791 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1803 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1812 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1821 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1822 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1827 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1828 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1830 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1831 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1834 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1835 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1852 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1853 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1855 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1856 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1861 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1862 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1886 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1887 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1892 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1897 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1898 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1909 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1910 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1912 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1913 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1916 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1917 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1986 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1987 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1993 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1994 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
2019 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2020 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2046 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
2047 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2049 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
2050 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2052 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
2053 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2055 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
2056 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2057 _ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
2058 _ASM_INSN32_IF_MM(0x0000017c));
2059 _ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
2060 _ASM_INSN32_IF_MM(0x0000117c));
2061 _ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
2062 _ASM_INSN32_IF_MM(0x0000217c));
2063 _ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
2064 _ASM_INSN32_IF_MM(0x0000317c));
2065 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2066 _ASM_INSN32_IF_MM(0x0000517c));
2078 "mfgc0\t%0, " #source ", %1\n\t" \
2091 "dmfgc0\t%0, " #source ", %1\n\t" \
2108 } while (0)
2120 } while (0)
2133 } while (0)
2135 #define read_gc0_index() __read_32bit_gc0_register($0, 0)
2136 #define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2138 #define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2139 #define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2141 #define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2142 #define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2144 #define read_gc0_context() __read_ulong_gc0_register($4, 0)
2145 #define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2156 #define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2157 #define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2180 #define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2181 #define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2186 #define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2187 #define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2189 #define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2190 #define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2198 #define read_gc0_count() __read_32bit_gc0_register($9, 0)
2200 #define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2201 #define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2203 #define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2204 #define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2206 #define read_gc0_status() __read_32bit_gc0_register($12, 0)
2207 #define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2212 #define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2213 #define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2215 #define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2216 #define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2218 #define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2226 #define read_gc0_config() __read_32bit_gc0_register($16, 0)
2234 #define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2243 #define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2244 #define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2246 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2254 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2263 #define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2271 #define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2280 #define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2281 #define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2283 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2284 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2308 #define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2309 #define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2351 " cfc1 %0,"STR(source)" \n" \
2363 " ctc1 %0,"STR(dest)" \n" \
2366 } while (0)
2389 " rddsp %0, %x1 \n" \
2402 " wrdsp %0, %x1 \n" \
2406 } while (0)
2415 " mflo %0, $ac0 \n" \
2428 " mflo %0, $ac1 \n" \
2441 " mflo %0, $ac2 \n" \
2454 " mflo %0, $ac3 \n" \
2467 " mfhi %0, $ac0 \n" \
2480 " mfhi %0, $ac1 \n" \
2493 " mfhi %0, $ac2 \n" \
2506 " mfhi %0, $ac3 \n" \
2519 " mtlo %0, $ac0 \n" \
2531 " mtlo %0, $ac1 \n" \
2543 " mtlo %0, $ac2 \n" \
2555 " mtlo %0, $ac3 \n" \
2567 " mthi %0, $ac0 \n" \
2579 " mthi %0, $ac1 \n" \
2591 " mthi %0, $ac2 \n" \
2603 " mthi %0, $ac3 \n" \
2619 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2620 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2621 " move %0, $1 \n" \
2633 " move $1, %0 \n" \
2635 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2636 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2640 } while (0)
2649 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2650 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2651 " move %0, $1 \n" \
2663 " move $1, %0 \n" \
2664 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2665 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2669 } while (0)
2673 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2674 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2676 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2677 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2681 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2682 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2684 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2685 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2689 #define mflo0() _dsp_mflo(0)
2694 #define mfhi0() _dsp_mfhi(0)
2699 #define mtlo0(x) _dsp_mtlo(x, 0)
2704 #define mthi0(x) _dsp_mthi(x, 0)
2727 int res = 0; in tlb_read()
2734 " .word 0x41610001 # dvpe $1 \n" in tlb_read()
2735 " move %0, $1 \n" in tlb_read()
2755 " .word 0x41600021 # evpe \n" in tlb_read()