Lines Matching +full:way +full:- +full:select

1 # SPDX-License-Identifier: GPL-2.0
4 # see Documentation/kbuild/kconfig-language.rst.
9 	select ARCH_32BIT_OFF_T
10 	select ARCH_HAS_DMA_SET_UNCACHED
11 	select ARCH_HAS_DMA_CLEAR_UNCACHED
12 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
13 	select OF
14 	select OF_EARLY_FLATTREE
15 	select IRQ_DOMAIN
16 	select HANDLE_DOMAIN_IRQ
17 	select GPIOLIB
18 	select HAVE_ARCH_TRACEHOOK
19 	select SPARSE_IRQ
20 	select GENERIC_IRQ_CHIP
21 	select GENERIC_IRQ_PROBE
22 	select GENERIC_IRQ_SHOW
23 	select GENERIC_IOMAP
24 	select GENERIC_CPU_DEVICES
25 	select HAVE_UID16
26 	select GENERIC_ATOMIC64
27 	select GENERIC_CLOCKEVENTS
28 	select GENERIC_CLOCKEVENTS_BROADCAST
29 	select GENERIC_STRNCPY_FROM_USER
30 	select GENERIC_STRNLEN_USER
31 	select GENERIC_SMP_IDLE_THREAD
32 	select MODULES_USE_ELF_RELA
33 	select HAVE_DEBUG_STACKOVERFLOW
34 	select OR1K_PIC
35 	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
36 	select ARCH_USE_QUEUED_SPINLOCKS
37 	select ARCH_USE_QUEUED_RWLOCKS
38 	select OMPIC if SMP
39 	select ARCH_WANT_FRAME_POINTERS
40 	select GENERIC_IRQ_MULTI_HANDLER
41 	select MMU_GATHER_NO_RANGE if MMU
42 	select SET_FS
87 	  Select this if your implementation features write through data caches.
89 	  caches at relevant times. Most OpenRISC implementations support write-
104 	  Select this if your implementation has the Class II instruction l.ff1
110 	  Select this if your implementation has the Class II instruction l.fl1
116 	  Select this if your implementation has a hardware multiply instruction
122 	  Select this if your implementation has a hardware divide instruction
126 	int "Maximum number of CPUs (2-32)"
132 	bool "Symmetric Multi-Processing support"
170 	  On some architectures there is currently no way for the boot loader
172 	  supply some command-line options at build time by entering them