Lines Matching +full:0 +full:xb
32 #define EFAPU 0x4
34 #define VCT 0x4
35 #define SPFP 0x6
36 #define DPFP 0x7
38 #define EFSADD 0x2c0
39 #define EFSSUB 0x2c1
40 #define EFSABS 0x2c4
41 #define EFSNABS 0x2c5
42 #define EFSNEG 0x2c6
43 #define EFSMUL 0x2c8
44 #define EFSDIV 0x2c9
45 #define EFSCMPGT 0x2cc
46 #define EFSCMPLT 0x2cd
47 #define EFSCMPEQ 0x2ce
48 #define EFSCFD 0x2cf
49 #define EFSCFSI 0x2d1
50 #define EFSCTUI 0x2d4
51 #define EFSCTSI 0x2d5
52 #define EFSCTUF 0x2d6
53 #define EFSCTSF 0x2d7
54 #define EFSCTUIZ 0x2d8
55 #define EFSCTSIZ 0x2da
57 #define EVFSADD 0x280
58 #define EVFSSUB 0x281
59 #define EVFSABS 0x284
60 #define EVFSNABS 0x285
61 #define EVFSNEG 0x286
62 #define EVFSMUL 0x288
63 #define EVFSDIV 0x289
64 #define EVFSCMPGT 0x28c
65 #define EVFSCMPLT 0x28d
66 #define EVFSCMPEQ 0x28e
67 #define EVFSCTUI 0x294
68 #define EVFSCTSI 0x295
69 #define EVFSCTUF 0x296
70 #define EVFSCTSF 0x297
71 #define EVFSCTUIZ 0x298
72 #define EVFSCTSIZ 0x29a
74 #define EFDADD 0x2e0
75 #define EFDSUB 0x2e1
76 #define EFDABS 0x2e4
77 #define EFDNABS 0x2e5
78 #define EFDNEG 0x2e6
79 #define EFDMUL 0x2e8
80 #define EFDDIV 0x2e9
81 #define EFDCTUIDZ 0x2ea
82 #define EFDCTSIDZ 0x2eb
83 #define EFDCMPGT 0x2ec
84 #define EFDCMPLT 0x2ed
85 #define EFDCMPEQ 0x2ee
86 #define EFDCFS 0x2ef
87 #define EFDCTUI 0x2f4
88 #define EFDCTSI 0x2f5
89 #define EFDCTUF 0x2f6
90 #define EFDCTSF 0x2f7
91 #define EFDCTUIZ 0x2f8
92 #define EFDCTSIZ 0x2fa
96 #define XB 4 macro
98 #define NOTYPE 0
116 switch (speinsn & 0x7ff) { in insn_type()
119 case EFSCFD: ret = XB; break; in insn_type()
123 case EFSCTSF: ret = XB; break; in insn_type()
124 case EFSCTSI: ret = XB; break; in insn_type()
125 case EFSCTSIZ: ret = XB; break; in insn_type()
126 case EFSCTUF: ret = XB; break; in insn_type()
127 case EFSCTUI: ret = XB; break; in insn_type()
128 case EFSCTUIZ: ret = XB; break; in insn_type()
134 case EFSCFSI: ret = XB; break; in insn_type()
141 case EVFSCTSF: ret = XB; break; in insn_type()
142 case EVFSCTSI: ret = XB; break; in insn_type()
143 case EVFSCTSIZ: ret = XB; break; in insn_type()
144 case EVFSCTUF: ret = XB; break; in insn_type()
145 case EVFSCTUI: ret = XB; break; in insn_type()
146 case EVFSCTUIZ: ret = XB; break; in insn_type()
155 case EFDCFS: ret = XB; break; in insn_type()
159 case EFDCTSF: ret = XB; break; in insn_type()
160 case EFDCTSI: ret = XB; break; in insn_type()
161 case EFDCTSIDZ: ret = XB; break; in insn_type()
162 case EFDCTSIZ: ret = XB; break; in insn_type()
163 case EFDCTUF: ret = XB; break; in insn_type()
164 case EFDCTUI: ret = XB; break; in insn_type()
165 case EFDCTUIDZ: ret = XB; break; in insn_type()
166 case EFDCTUIZ: ret = XB; break; in insn_type()
194 func = speinsn & 0x7ff; in do_spe_mathemu()
195 fc = (speinsn >> 21) & 0x1f; in do_spe_mathemu()
196 fa = (speinsn >> 16) & 0x1f; in do_spe_mathemu()
197 fb = (speinsn >> 11) & 0x1f; in do_spe_mathemu()
198 src = (speinsn >> 5) & 0x7; in do_spe_mathemu()
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
222 case XB: in do_spe_mathemu()
263 cmp = 0; in do_spe_mathemu()
277 vc.wp[1] = 0; in do_spe_mathemu()
301 vc.wp[1] = 0; in do_spe_mathemu()
305 ((func & 0x3) != 0)); in do_spe_mathemu()
312 vc.wp[1] = 0; in do_spe_mathemu()
316 ((func & 0x3) != 0)); in do_spe_mathemu()
336 IR = 0x4; in do_spe_mathemu()
338 IR = 0; in do_spe_mathemu()
350 case XB: in do_spe_mathemu()
365 vc.dp[0] = va.dp[0] & ~SIGN_BIT_D; in do_spe_mathemu()
369 vc.dp[0] = va.dp[0] | SIGN_BIT_D; in do_spe_mathemu()
373 vc.dp[0] = va.dp[0] ^ SIGN_BIT_D; in do_spe_mathemu()
393 cmp = 0; in do_spe_mathemu()
407 vc.wp[1] = 0; in do_spe_mathemu()
431 vc.dp[0] = 0; in do_spe_mathemu()
434 FP_TO_INT_D(vc.dp[0], DB, 64, in do_spe_mathemu()
435 ((func & 0x1) == 0)); in do_spe_mathemu()
442 vc.wp[1] = 0; in do_spe_mathemu()
446 ((func & 0x3) != 0)); in do_spe_mathemu()
453 vc.wp[1] = 0; in do_spe_mathemu()
457 ((func & 0x3) != 0)); in do_spe_mathemu()
478 IR = 0x4; in do_spe_mathemu()
480 IR = 0; in do_spe_mathemu()
496 case XB: in do_spe_mathemu()
517 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; in do_spe_mathemu()
522 vc.wp[0] = va.wp[0] | SIGN_BIT_S; in do_spe_mathemu()
527 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; in do_spe_mathemu()
552 cmp = 0; in do_spe_mathemu()
566 vc.wp[0] = 0; in do_spe_mathemu()
570 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
574 vc.wp[1] = 0; in do_spe_mathemu()
586 vc.wp[0] = 0; in do_spe_mathemu()
589 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
590 ((func & 0x3) != 0)); in do_spe_mathemu()
593 vc.wp[1] = 0; in do_spe_mathemu()
597 ((func & 0x3) != 0)); in do_spe_mathemu()
604 vc.wp[0] = 0; in do_spe_mathemu()
607 FP_TO_INT_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
608 ((func & 0x3) != 0)); in do_spe_mathemu()
611 vc.wp[1] = 0; in do_spe_mathemu()
615 ((func & 0x3) != 0)); in do_spe_mathemu()
644 ch = (IR0 == cmp) ? 1 : 0; in do_spe_mathemu()
645 cl = (IR1 == cmp) ? 1 : 0; in do_spe_mathemu()
647 ((ch & cl) << 0); in do_spe_mathemu()
656 regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2)); in do_spe_mathemu()
657 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2)); in do_spe_mathemu()
682 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
688 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
689 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
690 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
709 return 0; in do_spe_mathemu()
716 return 0; in do_spe_mathemu()
736 func = speinsn & 0x7ff; in speround_handler()
743 fptype = (speinsn >> 5) & 0x7; in speround_handler()
749 return 0; in speround_handler()
751 fc = (speinsn >> 21) & 0x1f; in speround_handler()
754 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
757 fb = (speinsn >> 11) & 0x1f; in speround_handler()
771 return 0; in speround_handler()
779 fp_result = 0; in speround_handler()
780 s_lo = 0; in speround_handler()
781 s_hi = 0; in speround_handler()
786 fp_result = 0; in speround_handler()
788 if (fgpr.wp[1] == 0) in speround_handler()
794 fp_result = 0; in speround_handler()
796 if (fgpr.wp[1] == 0) in speround_handler()
798 if (fgpr.wp[0] == 0) in speround_handler()
804 fp_result = 0; in speround_handler()
807 if (fgpr.wp[1] == 0) in speround_handler()
816 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
825 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
829 fgpr.wp[1]++; /* Z < 0, choose Z2 */ in speround_handler()
831 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
840 fgpr.dp[0]++; /* Z > 0, choose Z1 */ in speround_handler()
842 fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
847 fgpr.dp[0]++; /* Z < 0, choose Z2 */ in speround_handler()
849 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
857 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ in speround_handler()
859 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ in speround_handler()
863 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ in speround_handler()
865 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ in speround_handler()
869 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ in speround_handler()
871 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ in speround_handler()
880 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
883 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
886 return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0; in speround_handler()
887 return 0; in speround_handler()
925 return 0; in spe_mathemu_init()