34 # define TRAP_RESERVED_INST	4
86 				struct mem_access *ma)  in handle_unaligned_ins()  argument
96 	index = (instruction>>4)&15;	/* 0x00F0 */  in handle_unaligned_ins()
104 	case 4: inc_unaligned_dword_access(); break;  in handle_unaligned_ins()
119 			dst += 4-count;  in handle_unaligned_ins()
121 			if (ma->from(dst, srcu, count))  in handle_unaligned_ins()
129 			src += 4-count;  in handle_unaligned_ins()
134 			if (ma->to(dstu, src, count))  in handle_unaligned_ins()
145 		if (ma->to(dstu, src, 4))  in handle_unaligned_ins()
151 		if (instruction & 4)  in handle_unaligned_ins()
156 		src += 4-count;  in handle_unaligned_ins()
158 		if (ma->to(dstu, src, count))  in handle_unaligned_ins()
169 		if (ma->from(dst, srcu, 4))  in handle_unaligned_ins()
176 		if (instruction & 4)  in handle_unaligned_ins()
182 		dst += 4-count;  in handle_unaligned_ins()
184 		if (ma->from(dst, srcu, count))  in handle_unaligned_ins()
200 			if (ma->to(dstu, src, 2))  in handle_unaligned_ins()
214 			if (ma->from(dst, srcu, 2))  in handle_unaligned_ins()
224 		srcu += 4;  in handle_unaligned_ins()
233 		if (ma->from(dst, srcu, 2))  in handle_unaligned_ins()
241 		srcu += 4;  in handle_unaligned_ins()
246 		if (ma->from(dst, srcu, 4))  in handle_unaligned_ins()
267 				   struct mem_access *ma)  in handle_delayslot()  argument
283 	return handle_unaligned_ins(instruction, regs, ma);  in handle_delayslot()
299 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
300 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
303 			    struct mem_access *ma, int expected,  in handle_unaligned_access()  argument
336 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
342 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
344 				regs->pc += rm + 4;  in handle_unaligned_access()
348 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
350 				regs->pr = regs->pc + 4;  in handle_unaligned_access()
351 				regs->pc += rm + 4;  in handle_unaligned_access()
369 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
375 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
377 				regs->pr = regs->pc + 4;  in handle_unaligned_access()
403 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
407 					regs->pc += 4; /* next after slot */  in handle_unaligned_access()
417 			ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
421 					regs->pc += 4; /* next after slot */  in handle_unaligned_access()
434 		ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
440 		ret = handle_delayslot(regs, instruction, ma);  in handle_unaligned_access()
442 			regs->pr = regs->pc + 4;  in handle_unaligned_access()
454 	ret = handle_unaligned_ins(instruction, regs, ma);  in handle_unaligned_access()
649 	 * bfs: 8fxx: PC+=d*2+4;  in emulate_branch()
650 	 * bts: 8dxx: PC+=d*2+4;  in emulate_branch()
651 	 * bra: axxx: PC+=D*2+4;  in emulate_branch()
652 	 * bsr: bxxx: PC+=D*2+4  after PR=PC+4;  in emulate_branch()
653 	 * braf:0x23: PC+=Rn*2+4;  in emulate_branch()
654 	 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;  in emulate_branch()
655 	 * jmp: 4x2b: PC=Rn;  in emulate_branch()
656 	 * jsr: 4x0b: PC=Rn      after PR=PC+4;  in emulate_branch()
662 		regs->pr = regs->pc + 4;  in emulate_branch()
675 		regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;  in emulate_branch()
762 	 * For SH-4 lacking an FPU, treat floating point instructions as  in trap_init()