67 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)  in check_memory_type_self_snoop_errata()  argument
69 	switch (c->x86_model) {  in check_memory_type_self_snoop_errata()
95 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)  in probe_xeon_phi_r3mwait()  argument
101 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
103 	switch (c->x86_model) {  in probe_xeon_phi_r3mwait()
114 	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);  in probe_xeon_phi_r3mwait()
118 	if (c == &boot_cpu_data)  in probe_xeon_phi_r3mwait()
159 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)  in bad_spectre_microcode()  argument
167 	if (cpu_has(c, X86_FEATURE_HYPERVISOR))  in bad_spectre_microcode()
170 	if (c->x86 != 6)  in bad_spectre_microcode()
174 		if (c->x86_model == spectre_bad_microcodes[i].model &&  in bad_spectre_microcode()
175 		    c->x86_stepping == spectre_bad_microcodes[i].stepping)  in bad_spectre_microcode()
176 			return (c->microcode <= spectre_bad_microcodes[i].microcode);  in bad_spectre_microcode()
181 static void early_init_intel(struct cpuinfo_x86 *c)  in early_init_intel()  argument
186 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
189 			c->cpuid_level = cpuid_eax(0);  in early_init_intel()
190 			get_cpu_cap(c);  in early_init_intel()
194 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
195 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
196 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);  in early_init_intel()
198 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
199 		c->microcode = intel_get_microcode_revision();  in early_init_intel()
202 	if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||  in early_init_intel()
203 	     cpu_has(c, X86_FEATURE_INTEL_STIBP) ||  in early_init_intel()
204 	     cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||  in early_init_intel()
205 	     cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {  in early_init_intel()
225 	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&  in early_init_intel()
226 	    c->microcode < 0x20e) {  in early_init_intel()
228 		clear_cpu_cap(c, X86_FEATURE_PSE);  in early_init_intel()
232 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);  in early_init_intel()
235 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
236 		c->x86_cache_alignment = 128;  in early_init_intel()
240 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
241 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
242 		c->x86_phys_bits = 36;  in early_init_intel()
245 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_intel()
246 	 * with P/T states and does not stop in deep C-states.  in early_init_intel()
251 	if (c->x86_power & (1 << 8)) {  in early_init_intel()
252 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);  in early_init_intel()
253 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);  in early_init_intel()
257 	if (c->x86 == 6) {  in early_init_intel()
258 		switch (c->x86_model) {  in early_init_intel()
263 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);  in early_init_intel()
280 	if (c->x86 == 6 && c->x86_model < 15)  in early_init_intel()
281 		clear_cpu_cap(c, X86_FEATURE_PAT);  in early_init_intel()
287 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
306 	if (c->x86 == 5 && c->x86_model == 9) {  in early_init_intel()
311 	if (c->cpuid_level >= 0x00000001) {  in early_init_intel()
321 			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);  in early_init_intel()
324 	check_memory_type_self_snoop_errata(c);  in early_init_intel()
330 	if (detect_extended_topology_early(c) < 0)  in early_init_intel()
331 		detect_ht_early(c);  in early_init_intel()
334 static void bsp_init_intel(struct cpuinfo_x86 *c)  in bsp_init_intel()  argument
336 	resctrl_cpu_detect(c);  in bsp_init_intel()
359 static void intel_smp_check(struct cpuinfo_x86 *c)  in intel_smp_check()  argument
362 	if (!c->cpu_index)  in intel_smp_check()
368 	if (c->x86 == 5 &&  in intel_smp_check()
369 	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&  in intel_smp_check()
370 	    c->x86_model <= 3) {  in intel_smp_check()
387 static void intel_workarounds(struct cpuinfo_x86 *c)  in intel_workarounds()  argument
396 	clear_cpu_bug(c, X86_BUG_F00F);  in intel_workarounds()
397 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
400 		set_cpu_bug(c, X86_BUG_F00F);  in intel_workarounds()
412 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
413 		clear_cpu_cap(c, X86_FEATURE_SEP);  in intel_workarounds()
422 		set_cpu_cap(c, X86_FEATURE_PAE);  in intel_workarounds()
430 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
444 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
445 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
446 		set_cpu_bug(c, X86_BUG_11AP);  in intel_workarounds()
453 	switch (c->x86) {  in intel_workarounds()
454 	case 4:		/* 486: untested */  in intel_workarounds()
467 	intel_smp_check(c);  in intel_workarounds()
470 static void intel_workarounds(struct cpuinfo_x86 *c)  in intel_workarounds()  argument
475 static void srat_detect_node(struct cpuinfo_x86 *c)  in srat_detect_node()  argument
498 #define TME_ACTIVATE_POLICY(x)		((x >> 4) & 0xf)	/* Bits 7:4 */
512 static void detect_tme(struct cpuinfo_x86 *c)  in detect_tme()  argument
573 	c->x86_phys_bits -= keyid_bits;  in detect_tme()
576 static void init_cpuid_fault(struct cpuinfo_x86 *c)  in init_cpuid_fault()  argument
582 			set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);  in init_cpuid_fault()
586 static void init_intel_misc_features(struct cpuinfo_x86 *c)  in init_intel_misc_features()  argument
597 	init_cpuid_fault(c);  in init_intel_misc_features()
598 	probe_xeon_phi_r3mwait(c);  in init_intel_misc_features()
606 static void init_intel(struct cpuinfo_x86 *c)  in init_intel()  argument
608 	early_init_intel(c);  in init_intel()
610 	intel_workarounds(c);  in init_intel()
617 	detect_extended_topology(c);  in init_intel()
619 	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {  in init_intel()
624 		detect_num_cpu_cores(c);  in init_intel()
626 		detect_ht(c);  in init_intel()
630 	init_intel_cacheinfo(c);  in init_intel()
632 	if (c->cpuid_level > 9) {  in init_intel()
636 			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);  in init_intel()
639 	if (cpu_has(c, X86_FEATURE_XMM2))  in init_intel()
640 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);  in init_intel()
647 			set_cpu_cap(c, X86_FEATURE_BTS);  in init_intel()
649 			set_cpu_cap(c, X86_FEATURE_PEBS);  in init_intel()
652 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&  in init_intel()
653 	    (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))  in init_intel()
654 		set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);  in init_intel()
656 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&  in init_intel()
657 		((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))  in init_intel()
658 		set_cpu_bug(c, X86_BUG_MONITOR);  in init_intel()
661 	if (c->x86 == 15)  in init_intel()
662 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_intel()
663 	if (c->x86 == 6)  in init_intel()
664 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);  in init_intel()
671 	if (c->x86 == 6) {  in init_intel()
672 		unsigned int l2 = c->x86_cache_size;  in init_intel()
675 		switch (c->x86_model) {  in init_intel()
686 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
697 			strcpy(c->x86_model_id, p);  in init_intel()
700 	if (c->x86 == 15)  in init_intel()
701 		set_cpu_cap(c, X86_FEATURE_P4);  in init_intel()
702 	if (c->x86 == 6)  in init_intel()
703 		set_cpu_cap(c, X86_FEATURE_P3);  in init_intel()
707 	srat_detect_node(c);  in init_intel()
709 	init_ia32_feat_ctl(c);  in init_intel()
711 	if (cpu_has(c, X86_FEATURE_TME))  in init_intel()
712 		detect_tme(c);  in init_intel()
714 	init_intel_misc_features(c);  in init_intel()
725 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)  in intel_size_cache()  argument
733 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
737 	 * Intel Quark SoC X1000 contains a 4-way set associative  in intel_size_cache()
740 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
768 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
769 	{ 0x02, TLB_INST_4M,		2,	" TLB_INST 4 MByte pages, full associative" },
770 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
771 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
772 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
773 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
774 	{ 0x4f, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages" },
775 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
776 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
777 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
778 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
779 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
780 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
781 	{ 0x59, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, fully associative" },
782 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
783 	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
784 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
785 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
786 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
787 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
788 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
789 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
791 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
792 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
793 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
794 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
795 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
796 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
797 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
798 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
799 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
800 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
801 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
802 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
803 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
894 static void intel_detect_tlb(struct cpuinfo_x86 *c)  in intel_detect_tlb()  argument
897 	unsigned int regs[4];  in intel_detect_tlb()
900 	if (c->cpuid_level < 2)  in intel_detect_tlb()
925 		{ .family = 4, .model_names =
931 			  [4] = "486 SL",
934 			  [8] = "486 DX/4",
935 			  [9] = "486 DX/4-WB"
944 			  [4] = "Pentium MMX",
955 			  [4] = "Pentium II (Deschutes)",
966 			  [0] = "Pentium 4 (Unknown)",
967 			  [1] = "Pentium 4 (Willamette)",
968 			  [2] = "Pentium 4 (Northwood)",
969 			  [4] = "Pentium 4 (Foster)",
970 			  [5] = "Pentium 4 (Foster)",
1166 void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)  in cpu_set_core_cap_bits()  argument
1182 		if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))  in cpu_set_core_cap_bits()