Lines Matching +full:0 +full:x4090
30 * - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
32 * - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
33 * and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
35 * ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all
37 * - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
38 * of '0x67'.
156 .word 0
159 .quad 0x0000000000000000 /* NULL descriptor */
161 .quad GDT_ENTRY(0xa09a, 0, 0xfffff) /* PVH_CS_SEL */
163 .quad GDT_ENTRY(0xc09a, 0, 0xfffff) /* PVH_CS_SEL */
165 .quad GDT_ENTRY(0xc092, 0, 0xfffff) /* PVH_DS_SEL */
166 .quad GDT_ENTRY(0x4090, 0, 0x18) /* PVH_CANARY_SEL */
170 SYM_DATA_LOCAL(canary, .fill 48, 1, 0)
173 .fill BOOT_STACK_SIZE, 1, 0