Lines Matching +full:bypass +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
34 if (!map->num_reg_defaults_raw) in regcache_hw_init()
35 return -EINVAL; in regcache_hw_init()
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
39 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
40 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
43 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
45 map->cache_bypass = true; in regcache_hw_init()
49 map->num_reg_defaults = count; in regcache_hw_init()
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
52 if (!map->reg_defaults) in regcache_hw_init()
53 return -ENOMEM; in regcache_hw_init()
55 if (!map->reg_defaults_raw) { in regcache_hw_init()
56 bool cache_bypass = map->cache_bypass; in regcache_hw_init()
57 dev_warn(map->dev, "No cache defaults, reading back from HW\n"); in regcache_hw_init()
59 /* Bypass the cache access till data read from HW */ in regcache_hw_init()
60 map->cache_bypass = true; in regcache_hw_init()
61 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); in regcache_hw_init()
63 ret = -ENOMEM; in regcache_hw_init()
67 map->cache_size_raw); in regcache_hw_init()
68 map->cache_bypass = cache_bypass; in regcache_hw_init()
70 map->reg_defaults_raw = tmp_buf; in regcache_hw_init()
71 map->cache_free = 1; in regcache_hw_init()
78 for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { in regcache_hw_init()
79 reg = i * map->reg_stride; in regcache_hw_init()
87 if (map->reg_defaults_raw) { in regcache_hw_init()
88 val = regcache_get_val(map, map->reg_defaults_raw, i); in regcache_hw_init()
90 bool cache_bypass = map->cache_bypass; in regcache_hw_init()
92 map->cache_bypass = true; in regcache_hw_init()
94 map->cache_bypass = cache_bypass; in regcache_hw_init()
96 dev_err(map->dev, "Failed to read %d: %d\n", in regcache_hw_init()
102 map->reg_defaults[j].reg = reg; in regcache_hw_init()
103 map->reg_defaults[j].def = val; in regcache_hw_init()
110 kfree(map->reg_defaults); in regcache_hw_init()
121 if (map->cache_type == REGCACHE_NONE) { in regcache_init()
122 if (config->reg_defaults || config->num_reg_defaults_raw) in regcache_init()
123 dev_warn(map->dev, in regcache_init()
126 map->cache_bypass = true; in regcache_init()
130 if (config->reg_defaults && !config->num_reg_defaults) { in regcache_init()
131 dev_err(map->dev, in regcache_init()
133 return -EINVAL; in regcache_init()
136 for (i = 0; i < config->num_reg_defaults; i++) in regcache_init()
137 if (config->reg_defaults[i].reg % map->reg_stride) in regcache_init()
138 return -EINVAL; in regcache_init()
141 if (cache_types[i]->type == map->cache_type) in regcache_init()
145 dev_err(map->dev, "Could not match compress type: %d\n", in regcache_init()
146 map->cache_type); in regcache_init()
147 return -EINVAL; in regcache_init()
150 map->num_reg_defaults = config->num_reg_defaults; in regcache_init()
151 map->num_reg_defaults_raw = config->num_reg_defaults_raw; in regcache_init()
152 map->reg_defaults_raw = config->reg_defaults_raw; in regcache_init()
153 map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); in regcache_init()
154 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; in regcache_init()
156 map->cache = NULL; in regcache_init()
157 map->cache_ops = cache_types[i]; in regcache_init()
159 if (!map->cache_ops->read || in regcache_init()
160 !map->cache_ops->write || in regcache_init()
161 !map->cache_ops->name) in regcache_init()
162 return -EINVAL; in regcache_init()
168 if (config->reg_defaults) { in regcache_init()
169 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * in regcache_init()
172 return -ENOMEM; in regcache_init()
173 map->reg_defaults = tmp_buf; in regcache_init()
174 } else if (map->num_reg_defaults_raw) { in regcache_init()
182 if (map->cache_bypass) in regcache_init()
186 if (!map->max_register) in regcache_init()
187 map->max_register = map->num_reg_defaults_raw; in regcache_init()
189 if (map->cache_ops->init) { in regcache_init()
190 dev_dbg(map->dev, "Initializing %s cache\n", in regcache_init()
191 map->cache_ops->name); in regcache_init()
192 ret = map->cache_ops->init(map); in regcache_init()
199 kfree(map->reg_defaults); in regcache_init()
200 if (map->cache_free) in regcache_init()
201 kfree(map->reg_defaults_raw); in regcache_init()
208 if (map->cache_type == REGCACHE_NONE) in regcache_exit()
211 BUG_ON(!map->cache_ops); in regcache_exit()
213 kfree(map->reg_defaults); in regcache_exit()
214 if (map->cache_free) in regcache_exit()
215 kfree(map->reg_defaults_raw); in regcache_exit()
217 if (map->cache_ops->exit) { in regcache_exit()
218 dev_dbg(map->dev, "Destroying %s cache\n", in regcache_exit()
219 map->cache_ops->name); in regcache_exit()
220 map->cache_ops->exit(map); in regcache_exit()
225 * regcache_read - Fetch the value of a given register from the cache.
238 if (map->cache_type == REGCACHE_NONE) in regcache_read()
239 return -ENOSYS; in regcache_read()
241 BUG_ON(!map->cache_ops); in regcache_read()
244 ret = map->cache_ops->read(map, reg, value); in regcache_read()
252 return -EINVAL; in regcache_read()
256 * regcache_write - Set the value of a given register in the cache.
267 if (map->cache_type == REGCACHE_NONE) in regcache_write()
270 BUG_ON(!map->cache_ops); in regcache_write()
273 return map->cache_ops->write(map, reg, value); in regcache_write()
284 if (!map->no_sync_defaults) in regcache_reg_needs_sync()
289 if (ret >= 0 && val == map->reg_defaults[ret].def) in regcache_reg_needs_sync()
299 for (reg = min; reg <= max; reg += map->reg_stride) { in regcache_default_sync()
314 map->cache_bypass = true; in regcache_default_sync()
316 map->cache_bypass = false; in regcache_default_sync()
318 dev_err(map->dev, "Unable to sync register %#x. %d\n", in regcache_default_sync()
322 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); in regcache_default_sync()
329 * regcache_sync - Sync the register cache with the hardware.
344 bool bypass; in regcache_sync() local
346 if (WARN_ON(map->cache_type == REGCACHE_NONE)) in regcache_sync()
347 return -EINVAL; in regcache_sync()
349 BUG_ON(!map->cache_ops); in regcache_sync()
351 map->lock(map->lock_arg); in regcache_sync()
352 /* Remember the initial bypass state */ in regcache_sync()
353 bypass = map->cache_bypass; in regcache_sync()
354 dev_dbg(map->dev, "Syncing %s cache\n", in regcache_sync()
355 map->cache_ops->name); in regcache_sync()
356 name = map->cache_ops->name; in regcache_sync()
359 if (!map->cache_dirty) in regcache_sync()
362 map->async = true; in regcache_sync()
365 map->cache_bypass = true; in regcache_sync()
366 for (i = 0; i < map->patch_regs; i++) { in regcache_sync()
367 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); in regcache_sync()
369 dev_err(map->dev, "Failed to write %x = %x: %d\n", in regcache_sync()
370 map->patch[i].reg, map->patch[i].def, ret); in regcache_sync()
374 map->cache_bypass = false; in regcache_sync()
376 if (map->cache_ops->sync) in regcache_sync()
377 ret = map->cache_ops->sync(map, 0, map->max_register); in regcache_sync()
379 ret = regcache_default_sync(map, 0, map->max_register); in regcache_sync()
382 map->cache_dirty = false; in regcache_sync()
385 /* Restore the bypass state */ in regcache_sync()
386 map->async = false; in regcache_sync()
387 map->cache_bypass = bypass; in regcache_sync()
388 map->no_sync_defaults = false; in regcache_sync()
389 map->unlock(map->lock_arg); in regcache_sync()
400 * regcache_sync_region - Sync part of the register cache with the hardware.
406 * Write all non-default register values in the specified region to
416 bool bypass; in regcache_sync_region() local
418 if (WARN_ON(map->cache_type == REGCACHE_NONE)) in regcache_sync_region()
419 return -EINVAL; in regcache_sync_region()
421 BUG_ON(!map->cache_ops); in regcache_sync_region()
423 map->lock(map->lock_arg); in regcache_sync_region()
425 /* Remember the initial bypass state */ in regcache_sync_region()
426 bypass = map->cache_bypass; in regcache_sync_region()
428 name = map->cache_ops->name; in regcache_sync_region()
429 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); in regcache_sync_region()
433 if (!map->cache_dirty) in regcache_sync_region()
436 map->async = true; in regcache_sync_region()
438 if (map->cache_ops->sync) in regcache_sync_region()
439 ret = map->cache_ops->sync(map, min, max); in regcache_sync_region()
444 /* Restore the bypass state */ in regcache_sync_region()
445 map->cache_bypass = bypass; in regcache_sync_region()
446 map->async = false; in regcache_sync_region()
447 map->no_sync_defaults = false; in regcache_sync_region()
448 map->unlock(map->lock_arg); in regcache_sync_region()
459 * regcache_drop_region - Discard part of the register cache
474 if (!map->cache_ops || !map->cache_ops->drop) in regcache_drop_region()
475 return -EINVAL; in regcache_drop_region()
477 map->lock(map->lock_arg); in regcache_drop_region()
481 ret = map->cache_ops->drop(map, min, max); in regcache_drop_region()
483 map->unlock(map->lock_arg); in regcache_drop_region()
490 * regcache_cache_only - Put a register map into cache only mode
493 * @enable: flag if changes should be written to the hardware
501 void regcache_cache_only(struct regmap *map, bool enable) in regcache_cache_only() argument
503 map->lock(map->lock_arg); in regcache_cache_only()
504 WARN_ON(map->cache_bypass && enable); in regcache_cache_only()
505 map->cache_only = enable; in regcache_cache_only()
506 trace_regmap_cache_only(map, enable); in regcache_cache_only()
507 map->unlock(map->lock_arg); in regcache_cache_only()
512 * regcache_mark_dirty - Indicate that HW registers were reset to default values
517 * on resume, regcache_sync() knows to write out all non-default values
526 map->lock(map->lock_arg); in regcache_mark_dirty()
527 map->cache_dirty = true; in regcache_mark_dirty()
528 map->no_sync_defaults = true; in regcache_mark_dirty()
529 map->unlock(map->lock_arg); in regcache_mark_dirty()
534 * regcache_cache_bypass - Put a register map into cache bypass mode
537 * @enable: flag if changes should not be written to the cache
539 * When a register map is marked with the cache bypass option, writes
544 void regcache_cache_bypass(struct regmap *map, bool enable) in regcache_cache_bypass() argument
546 map->lock(map->lock_arg); in regcache_cache_bypass()
547 WARN_ON(map->cache_only && enable); in regcache_cache_bypass()
548 map->cache_bypass = enable; in regcache_cache_bypass()
549 trace_regmap_cache_bypass(map, enable); in regcache_cache_bypass()
550 map->unlock(map->lock_arg); in regcache_cache_bypass()
561 if (map->format.format_val) { in regcache_set_val()
562 map->format.format_val(base + (map->cache_word_size * idx), in regcache_set_val()
567 switch (map->cache_word_size) { in regcache_set_val()
604 return -EINVAL; in regcache_get_val()
607 if (map->format.parse_val) in regcache_get_val()
608 return map->format.parse_val(regcache_get_val_addr(map, base, in regcache_get_val()
611 switch (map->cache_word_size) { in regcache_get_val()
638 return -1; in regcache_get_val()
646 return _a->reg - _b->reg; in regcache_default_cmp()
657 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, in regcache_lookup_reg()
661 return r - map->reg_defaults; in regcache_lookup_reg()
663 return -ENOENT; in regcache_lookup_reg()
683 regtmp = block_base + (i * map->reg_stride); in regcache_sync_block_single()
693 map->cache_bypass = true; in regcache_sync_block_single()
697 map->cache_bypass = false; in regcache_sync_block_single()
699 dev_err(map->dev, "Unable to sync register %#x. %d\n", in regcache_sync_block_single()
703 dev_dbg(map->dev, "Synced register %#x, value %#x\n", in regcache_sync_block_single()
713 size_t val_bytes = map->format.val_bytes; in regcache_sync_block_raw_flush()
719 count = (cur - base) / map->reg_stride; in regcache_sync_block_raw_flush()
721 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", in regcache_sync_block_raw_flush()
722 count * val_bytes, count, base, cur - map->reg_stride); in regcache_sync_block_raw_flush()
724 map->cache_bypass = true; in regcache_sync_block_raw_flush()
728 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", in regcache_sync_block_raw_flush()
729 base, cur - map->reg_stride, ret); in regcache_sync_block_raw_flush()
731 map->cache_bypass = false; in regcache_sync_block_raw_flush()
750 regtmp = block_base + (i * map->reg_stride); in regcache_sync_block_raw()
777 map->reg_stride); in regcache_sync_block_raw()
785 if (regmap_can_raw_write(map) && !map->use_single_write) in regcache_sync_block()