Lines Matching +full:clkout +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
101 return regmap_bulk_read(drvdata->regmap, reg, buf, count); in si5351_bulk_read()
107 return regmap_write(drvdata->regmap, reg, val); in si5351_reg_write()
113 return regmap_raw_write(drvdata->regmap, reg, buf, count); in si5351_bulk_write()
119 return regmap_update_bits(drvdata->regmap, reg, mask, val); in si5351_set_bits()
125 return SI5351_CLK6_PARAMETERS + (num - 6); in si5351_msynth_params_address()
138 params->p1 = buf[0]; in si5351_read_parameters()
139 params->p2 = 0; in si5351_read_parameters()
140 params->p3 = 1; in si5351_read_parameters()
144 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; in si5351_read_parameters()
145 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7]; in si5351_read_parameters()
146 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1]; in si5351_read_parameters()
148 params->valid = 1; in si5351_read_parameters()
159 buf[0] = params->p1 & 0xff; in si5351_write_parameters()
163 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
164 buf[1] = params->p3 & 0xff; in si5351_write_parameters()
167 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; in si5351_write_parameters()
168 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
169 buf[4] = params->p1 & 0xff; in si5351_write_parameters()
170 buf[5] = ((params->p3 & 0xf0000) >> 12) | in si5351_write_parameters()
171 ((params->p2 & 0xf0000) >> 16); in si5351_write_parameters()
172 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
173 buf[7] = params->p2 & 0xff; in si5351_write_parameters()
200 /* read-only */ in si5351_regmap_is_writeable()
216 * Si5351 xtal clock input
241 * Si5351 clkin clock input (Si5351C only)
261 * CMOS clock source constraints:
290 dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n", in si5351_clkin_recalc_rate()
303 * Si5351 vxco clock input (Si5351B only)
311 dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n"); in si5351_vxco_prepare()
351 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
352 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
358 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
374 return -EINVAL; in _si5351_pll_reparent()
376 if (drvdata->variant != SI5351_VARIANT_C && in _si5351_pll_reparent()
378 return -EINVAL; in _si5351_pll_reparent()
389 u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; in si5351_pll_get_parent()
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); in si5351_pll_get_parent()
402 if (hwdata->drvdata->variant != SI5351_VARIANT_C && in si5351_pll_set_parent()
404 return -EPERM; in si5351_pll_set_parent()
407 return -EINVAL; in si5351_pll_set_parent()
409 return _si5351_pll_reparent(hwdata->drvdata, hwdata->num, in si5351_pll_set_parent()
419 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : in si5351_pll_recalc_rate()
423 if (!hwdata->params.valid) in si5351_pll_recalc_rate()
424 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_pll_recalc_rate()
426 if (hwdata->params.p3 == 0) in si5351_pll_recalc_rate()
430 rate = hwdata->params.p1 * hwdata->params.p3; in si5351_pll_recalc_rate()
431 rate += 512 * hwdata->params.p3; in si5351_pll_recalc_rate()
432 rate += hwdata->params.p2; in si5351_pll_recalc_rate()
434 do_div(rate, 128 * hwdata->params.p3); in si5351_pll_recalc_rate()
436 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_recalc_rate()
437 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_recalc_rate()
439 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_pll_recalc_rate()
480 hwdata->params.p3 = c; in si5351_pll_round_rate()
481 hwdata->params.p2 = (128 * b) % c; in si5351_pll_round_rate()
482 hwdata->params.p1 = 128 * a; in si5351_pll_round_rate()
483 hwdata->params.p1 += (128 * b / c); in si5351_pll_round_rate()
484 hwdata->params.p1 -= 512; in si5351_pll_round_rate()
494 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_round_rate()
495 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_round_rate()
507 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : in si5351_pll_set_rate()
511 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_pll_set_rate()
514 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num, in si5351_pll_set_rate()
516 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); in si5351_pll_set_rate()
519 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, in si5351_pll_set_rate()
520 hwdata->num == 0 ? SI5351_PLL_RESET_A : in si5351_pll_set_rate()
523 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_set_rate()
524 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_set_rate()
526 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_pll_set_rate()
550 * Output Clock Multisynth Register Equations
552 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
553 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
570 return -EINVAL; in _si5351_msynth_reparent()
584 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); in si5351_msynth_get_parent()
594 return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num, in si5351_msynth_set_parent()
604 u8 reg = si5351_msynth_params_address(hwdata->num); in si5351_msynth_recalc_rate()
608 if (!hwdata->params.valid) in si5351_msynth_recalc_rate()
609 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_msynth_recalc_rate()
612 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3) in si5351_msynth_recalc_rate()
613 * multisync6-7: fOUT = fIN / P1 in si5351_msynth_recalc_rate()
616 if (hwdata->num > 5) { in si5351_msynth_recalc_rate()
617 m = hwdata->params.p1; in si5351_msynth_recalc_rate()
618 } else if (hwdata->params.p3 == 0) { in si5351_msynth_recalc_rate()
620 } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & in si5351_msynth_recalc_rate()
624 rate *= 128 * hwdata->params.p3; in si5351_msynth_recalc_rate()
625 m = hwdata->params.p1 * hwdata->params.p3; in si5351_msynth_recalc_rate()
626 m += hwdata->params.p2; in si5351_msynth_recalc_rate()
627 m += 512 * hwdata->params.p3; in si5351_msynth_recalc_rate()
634 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_recalc_rate()
635 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", in si5351_msynth_recalc_rate()
637 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_msynth_recalc_rate()
652 /* multisync6-7 can only handle freqencies < 150MHz */ in si5351_msynth_round_rate()
653 if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ) in si5351_msynth_round_rate()
683 } else if (hwdata->num >= 6) { in si5351_msynth_round_rate()
732 hwdata->params.p3 = 1; in si5351_msynth_round_rate()
733 hwdata->params.p2 = 0; in si5351_msynth_round_rate()
734 hwdata->params.p1 = 0; in si5351_msynth_round_rate()
735 } else if (hwdata->num >= 6) { in si5351_msynth_round_rate()
736 hwdata->params.p3 = 0; in si5351_msynth_round_rate()
737 hwdata->params.p2 = 0; in si5351_msynth_round_rate()
738 hwdata->params.p1 = a; in si5351_msynth_round_rate()
740 hwdata->params.p3 = c; in si5351_msynth_round_rate()
741 hwdata->params.p2 = (128 * b) % c; in si5351_msynth_round_rate()
742 hwdata->params.p1 = 128 * a; in si5351_msynth_round_rate()
743 hwdata->params.p1 += (128 * b / c); in si5351_msynth_round_rate()
744 hwdata->params.p1 -= 512; in si5351_msynth_round_rate()
747 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_round_rate()
748 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", in si5351_msynth_round_rate()
760 u8 reg = si5351_msynth_params_address(hwdata->num); in si5351_msynth_set_rate()
764 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_msynth_set_rate()
769 /* enable/disable integer mode and divby4 on multisynth0-5 */ in si5351_msynth_set_rate()
770 if (hwdata->num < 6) { in si5351_msynth_set_rate()
771 si5351_set_bits(hwdata->drvdata, reg + 2, in si5351_msynth_set_rate()
774 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_msynth_set_rate()
776 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); in si5351_msynth_set_rate()
779 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_set_rate()
780 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", in si5351_msynth_set_rate()
782 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_msynth_set_rate()
797 * Si5351 clkout divider
805 return -EINVAL; in _si5351_clkout_reparent()
822 if (drvdata->variant != SI5351_VARIANT_C) in _si5351_clkout_reparent()
823 return -EINVAL; in _si5351_clkout_reparent()
843 return -EINVAL; in _si5351_clkout_set_drive_strength()
873 u8 shift = (num < 4) ? (2 * num) : (2 * (num-4)); in _si5351_clkout_set_disable_state()
878 return -EINVAL; in _si5351_clkout_set_disable_state()
916 dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n", in _si5351_clkout_reset_pll()
917 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
926 hwdata->drvdata->client->dev.platform_data; in si5351_clkout_prepare()
928 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_prepare()
932 * Do a pll soft reset on the parent pll -- needed to get a in si5351_clkout_prepare()
935 if (pdata->clkout[hwdata->num].pll_reset) in si5351_clkout_prepare()
936 _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num); in si5351_clkout_prepare()
938 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, in si5351_clkout_prepare()
939 (1 << hwdata->num), 0); in si5351_clkout_prepare()
948 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_unprepare()
950 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, in si5351_clkout_unprepare()
951 (1 << hwdata->num), (1 << hwdata->num)); in si5351_clkout_unprepare()
961 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); in si5351_clkout_get_parent()
1001 return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent); in si5351_clkout_set_parent()
1012 if (hwdata->num <= 5) in si5351_clkout_recalc_rate()
1013 reg = si5351_msynth_params_address(hwdata->num) + 2; in si5351_clkout_recalc_rate()
1017 rdiv = si5351_reg_read(hwdata->drvdata, reg); in si5351_clkout_recalc_rate()
1018 if (hwdata->num == 6) { in si5351_clkout_recalc_rate()
1036 if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ) in si5351_clkout_round_rate()
1039 /* clkout freqency is 8kHz - 160MHz */ in si5351_clkout_round_rate()
1061 err = abs(new_rate - rate); in si5351_clkout_round_rate()
1064 new_err = abs(new_rate - rate); in si5351_clkout_round_rate()
1073 dev_dbg(&hwdata->drvdata->client->dev, in si5351_clkout_round_rate()
1074 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", in si5351_clkout_round_rate()
1092 err = abs(new_rate - rate); in si5351_clkout_set_rate()
1095 new_err = abs(new_rate - rate); in si5351_clkout_set_rate()
1103 switch (hwdata->num) { in si5351_clkout_set_rate()
1105 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, in si5351_clkout_set_rate()
1109 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, in si5351_clkout_set_rate()
1114 si5351_set_bits(hwdata->drvdata, in si5351_clkout_set_rate()
1115 si5351_msynth_params_address(hwdata->num) + 2, in si5351_clkout_set_rate()
1120 /* powerup clkout */ in si5351_clkout_set_rate()
1121 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_set_rate()
1124 dev_dbg(&hwdata->drvdata->client->dev, in si5351_clkout_set_rate()
1125 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", in si5351_clkout_set_rate()
1148 { .compatible = "silabs,si5351a-msop",
1159 struct device_node *child, *np = client->dev.of_node; in si5351_dt_parse()
1169 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); in si5351_dt_parse()
1171 return -ENOMEM; in si5351_dt_parse()
1174 * property silabs,pll-source : <num src>, [<..>] in si5351_dt_parse()
1177 of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) { in si5351_dt_parse()
1179 dev_err(&client->dev, in si5351_dt_parse()
1180 "invalid pll %d on pll-source prop\n", num); in si5351_dt_parse()
1181 return -EINVAL; in si5351_dt_parse()
1186 dev_err(&client->dev, in si5351_dt_parse()
1187 "missing pll-source for pll %d\n", num); in si5351_dt_parse()
1188 return -EINVAL; in si5351_dt_parse()
1193 pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; in si5351_dt_parse()
1197 dev_err(&client->dev, in si5351_dt_parse()
1200 return -EINVAL; in si5351_dt_parse()
1202 pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN; in si5351_dt_parse()
1205 dev_err(&client->dev, in si5351_dt_parse()
1207 return -EINVAL; in si5351_dt_parse()
1211 /* per clkout properties */ in si5351_dt_parse()
1214 dev_err(&client->dev, "missing reg property of %pOFn\n", in si5351_dt_parse()
1221 dev_err(&client->dev, "invalid clkout %d\n", num); in si5351_dt_parse()
1225 if (!of_property_read_u32(child, "silabs,multisynth-source", in si5351_dt_parse()
1229 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
1233 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
1237 dev_err(&client->dev, in si5351_dt_parse()
1244 if (!of_property_read_u32(child, "silabs,clock-source", &val)) { in si5351_dt_parse()
1247 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1251 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1255 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1260 dev_err(&client->dev, in si5351_dt_parse()
1261 "invalid parent %d for clkout %d\n", in si5351_dt_parse()
1265 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1269 dev_err(&client->dev, in si5351_dt_parse()
1270 "invalid parent %d for clkout %d\n", in si5351_dt_parse()
1276 if (!of_property_read_u32(child, "silabs,drive-strength", in si5351_dt_parse()
1283 pdata->clkout[num].drive = val; in si5351_dt_parse()
1286 dev_err(&client->dev, in si5351_dt_parse()
1287 "invalid drive strength %d for clkout %d\n", in si5351_dt_parse()
1293 if (!of_property_read_u32(child, "silabs,disable-state", in si5351_dt_parse()
1297 pdata->clkout[num].disable_state = in si5351_dt_parse()
1301 pdata->clkout[num].disable_state = in si5351_dt_parse()
1305 pdata->clkout[num].disable_state = in si5351_dt_parse()
1309 pdata->clkout[num].disable_state = in si5351_dt_parse()
1313 dev_err(&client->dev, in si5351_dt_parse()
1314 "invalid disable state %d for clkout %d\n", in si5351_dt_parse()
1320 if (!of_property_read_u32(child, "clock-frequency", &val)) in si5351_dt_parse()
1321 pdata->clkout[num].rate = val; in si5351_dt_parse()
1323 pdata->clkout[num].pll_master = in si5351_dt_parse()
1324 of_property_read_bool(child, "silabs,pll-master"); in si5351_dt_parse()
1326 pdata->clkout[num].pll_reset = in si5351_dt_parse()
1327 of_property_read_bool(child, "silabs,pll-reset"); in si5351_dt_parse()
1329 client->dev.platform_data = pdata; in si5351_dt_parse()
1334 return -EINVAL; in si5351_dt_parse()
1341 unsigned int idx = clkspec->args[0]; in si53351_of_clk_get()
1343 if (idx >= drvdata->num_clkout) { in si53351_of_clk_get()
1345 return ERR_PTR(-EINVAL); in si53351_of_clk_get()
1348 return &drvdata->clkout[idx].hw; in si53351_of_clk_get()
1366 enum si5351_variant variant = (enum si5351_variant)id->driver_data; in si5351_i2c_probe()
1378 pdata = client->dev.platform_data; in si5351_i2c_probe()
1380 return -EINVAL; in si5351_i2c_probe()
1382 drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL); in si5351_i2c_probe()
1384 return -ENOMEM; in si5351_i2c_probe()
1387 drvdata->client = client; in si5351_i2c_probe()
1388 drvdata->variant = variant; in si5351_i2c_probe()
1389 drvdata->pxtal = devm_clk_get(&client->dev, "xtal"); in si5351_i2c_probe()
1390 drvdata->pclkin = devm_clk_get(&client->dev, "clkin"); in si5351_i2c_probe()
1392 if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER || in si5351_i2c_probe()
1393 PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER) in si5351_i2c_probe()
1394 return -EPROBE_DEFER; in si5351_i2c_probe()
1397 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL, in si5351_i2c_probe()
1400 if (IS_ERR(drvdata->pxtal) && in si5351_i2c_probe()
1401 (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) { in si5351_i2c_probe()
1402 dev_err(&client->dev, "missing parent clock\n"); in si5351_i2c_probe()
1403 return -EINVAL; in si5351_i2c_probe()
1406 drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); in si5351_i2c_probe()
1407 if (IS_ERR(drvdata->regmap)) { in si5351_i2c_probe()
1408 dev_err(&client->dev, "failed to allocate register map\n"); in si5351_i2c_probe()
1409 return PTR_ERR(drvdata->regmap); in si5351_i2c_probe()
1415 if (drvdata->variant != SI5351_VARIANT_C) in si5351_i2c_probe()
1419 /* setup clock configuration */ in si5351_i2c_probe()
1421 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]); in si5351_i2c_probe()
1423 dev_err(&client->dev, in si5351_i2c_probe()
1425 n, pdata->pll_src[n]); in si5351_i2c_probe()
1432 pdata->clkout[n].multisynth_src); in si5351_i2c_probe()
1434 dev_err(&client->dev, in si5351_i2c_probe()
1436 n, pdata->clkout[n].multisynth_src); in si5351_i2c_probe()
1441 pdata->clkout[n].clkout_src); in si5351_i2c_probe()
1443 dev_err(&client->dev, in si5351_i2c_probe()
1444 "failed to reparent clkout %d to %d\n", in si5351_i2c_probe()
1445 n, pdata->clkout[n].clkout_src); in si5351_i2c_probe()
1450 pdata->clkout[n].drive); in si5351_i2c_probe()
1452 dev_err(&client->dev, in si5351_i2c_probe()
1453 "failed set drive strength of clkout%d to %d\n", in si5351_i2c_probe()
1454 n, pdata->clkout[n].drive); in si5351_i2c_probe()
1459 pdata->clkout[n].disable_state); in si5351_i2c_probe()
1461 dev_err(&client->dev, in si5351_i2c_probe()
1462 "failed set disable state of clkout%d to %d\n", in si5351_i2c_probe()
1463 n, pdata->clkout[n].disable_state); in si5351_i2c_probe()
1468 /* register xtal input clock gate */ in si5351_i2c_probe()
1473 if (!IS_ERR(drvdata->pxtal)) { in si5351_i2c_probe()
1474 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal); in si5351_i2c_probe()
1475 init.parent_names = &drvdata->pxtal_name; in si5351_i2c_probe()
1478 drvdata->xtal.init = &init; in si5351_i2c_probe()
1479 ret = devm_clk_hw_register(&client->dev, &drvdata->xtal); in si5351_i2c_probe()
1481 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1485 /* register clkin input clock gate */ in si5351_i2c_probe()
1486 if (drvdata->variant == SI5351_VARIANT_C) { in si5351_i2c_probe()
1490 if (!IS_ERR(drvdata->pclkin)) { in si5351_i2c_probe()
1491 drvdata->pclkin_name = __clk_get_name(drvdata->pclkin); in si5351_i2c_probe()
1492 init.parent_names = &drvdata->pclkin_name; in si5351_i2c_probe()
1495 drvdata->clkin.init = &init; in si5351_i2c_probe()
1496 ret = devm_clk_hw_register(&client->dev, &drvdata->clkin); in si5351_i2c_probe()
1498 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1505 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1; in si5351_i2c_probe()
1510 drvdata->pll[0].num = 0; in si5351_i2c_probe()
1511 drvdata->pll[0].drvdata = drvdata; in si5351_i2c_probe()
1512 drvdata->pll[0].hw.init = &init; in si5351_i2c_probe()
1519 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw); in si5351_i2c_probe()
1521 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1526 drvdata->pll[1].num = 1; in si5351_i2c_probe()
1527 drvdata->pll[1].drvdata = drvdata; in si5351_i2c_probe()
1528 drvdata->pll[1].hw.init = &init; in si5351_i2c_probe()
1530 if (drvdata->variant == SI5351_VARIANT_B) { in si5351_i2c_probe()
1543 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw); in si5351_i2c_probe()
1545 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1550 num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8; in si5351_i2c_probe()
1552 if (drvdata->variant == SI5351_VARIANT_B) in si5351_i2c_probe()
1557 drvdata->msynth = devm_kcalloc(&client->dev, num_clocks, in si5351_i2c_probe()
1558 sizeof(*drvdata->msynth), GFP_KERNEL); in si5351_i2c_probe()
1559 drvdata->clkout = devm_kcalloc(&client->dev, num_clocks, in si5351_i2c_probe()
1560 sizeof(*drvdata->clkout), GFP_KERNEL); in si5351_i2c_probe()
1561 drvdata->num_clkout = num_clocks; in si5351_i2c_probe()
1563 if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) { in si5351_i2c_probe()
1564 ret = -ENOMEM; in si5351_i2c_probe()
1569 drvdata->msynth[n].num = n; in si5351_i2c_probe()
1570 drvdata->msynth[n].drvdata = drvdata; in si5351_i2c_probe()
1571 drvdata->msynth[n].hw.init = &init; in si5351_i2c_probe()
1576 if (pdata->clkout[n].pll_master) in si5351_i2c_probe()
1580 ret = devm_clk_hw_register(&client->dev, in si5351_i2c_probe()
1581 &drvdata->msynth[n].hw); in si5351_i2c_probe()
1583 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1589 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3; in si5351_i2c_probe()
1597 drvdata->clkout[n].num = n; in si5351_i2c_probe()
1598 drvdata->clkout[n].drvdata = drvdata; in si5351_i2c_probe()
1599 drvdata->clkout[n].hw.init = &init; in si5351_i2c_probe()
1604 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N) in si5351_i2c_probe()
1608 ret = devm_clk_hw_register(&client->dev, in si5351_i2c_probe()
1609 &drvdata->clkout[n].hw); in si5351_i2c_probe()
1611 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1616 /* set initial clkout rate */ in si5351_i2c_probe()
1617 if (pdata->clkout[n].rate != 0) { in si5351_i2c_probe()
1619 ret = clk_set_rate(drvdata->clkout[n].hw.clk, in si5351_i2c_probe()
1620 pdata->clkout[n].rate); in si5351_i2c_probe()
1622 dev_err(&client->dev, "Cannot set rate : %d\n", in si5351_i2c_probe()
1628 ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get, in si5351_i2c_probe()
1631 dev_err(&client->dev, "unable to add clk provider\n"); in si5351_i2c_probe()
1640 of_clk_del_provider(client->dev.of_node); in si5351_i2c_remove()
1647 { "si5351a-msop", SI5351_VARIANT_A3 },
1666 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");