Lines Matching +full:control +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5  * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18  * struct ingenic_cgu_pll_info - information about a PLL
19  * @reg: the offset of the PLL's control register within the CGU
22  *           index of the lowest bit of the multiplier value in the PLL's
23  *           control register)
25  * @m_offset: the multiplier value which encodes to 0 in the PLL's control
28  *           index of the lowest bit of the divider value in the PLL's
29  *           control register)
31  * @n_offset: the divider value which encodes to 0 in the PLL's control
33  * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34  *            the index of the lowest bit of the post-VCO divider value in
35  *            the PLL's control register)
36  * @od_bits: the size of the post-VCO divider field in bits
37  * @od_max: the maximum post-VCO divider value
38  * @od_encoding: a pointer to an array mapping post-VCO divider values to
39  *               their encoded values in the PLL control register, or -1 for
41  * @bypass_reg: the offset of the bypass control register within the CGU
42  * @bypass_bit: the index of the bypass bit in the PLL control register
43  * @enable_bit: the index of the enable bit in the PLL control register
44  * @stable_bit: the index of the stable bit in the PLL control register
62  * struct ingenic_cgu_mux_info - information about a clock mux
63  * @reg: offset of the mux control register within the CGU
65  *         the lowest bit of the mux value within its control register)
75  * struct ingenic_cgu_div_info - information about a divider
76  * @reg: offset of the divider control register within the CGU
78  *         the lowest bit of the divide value within its control register)
83  * @ce_bit: the index of the change enable bit within reg, or -1 if there
85  * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
86  * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
102  * struct ingenic_cgu_fixdiv_info - information about a fixed divider
110  * struct ingenic_cgu_gate_info - information about a clock gate
111  * @reg: offset of the gate control register within the CGU
112  * @bit: offset of the bit in the register that controls the gate
113  * @clear_to_gate: if set, the clock is gated when the bit is cleared
118 	u8 bit;  member
124  * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
132  * struct ingenic_cgu_clk_info - information about a clock
136  *           within the clock_info array of the CGU, or -1 in entries
150 		CGU_CLK_EXT		= BIT(0),
151 		CGU_CLK_PLL		= BIT(1),
152 		CGU_CLK_GATE		= BIT(2),
153 		CGU_CLK_MUX		= BIT(3),
154 		CGU_CLK_MUX_GLITCHFREE	= BIT(4),
155 		CGU_CLK_DIV		= BIT(5),
156 		CGU_CLK_FIXDIV		= BIT(6),
157 		CGU_CLK_CUSTOM		= BIT(7),
177  * struct ingenic_cgu - data about the CGU
195  * struct ingenic_clk - private data for a clock
196  * @hw: see Documentation/driver-api/clk.rst
198  * @idx: the index of this clock in cgu->clock_info
209  * ingenic_cgu_new() - create a new CGU instance
223  * ingenic_cgu_register_clocks() - Registers the clocks
228  * Return: 0 on success or -errno if unsuccesful.