Lines Matching +full:0 +full:x4038
46 { P_XO, 0 },
60 { P_XO, 0 },
78 { P_XO, 0 },
94 { P_XO, 0 },
110 { P_XO, 0 },
126 { P_XO, 0 },
144 { P_XO, 0 },
162 { P_XO, 0 },
180 .l_reg = 0x0004,
181 .m_reg = 0x0008,
182 .n_reg = 0x000c,
183 .config_reg = 0x0014,
184 .mode_reg = 0x0000,
185 .status_reg = 0x001c,
196 .enable_reg = 0x0100,
197 .enable_mask = BIT(0),
207 .l_reg = 0x0044,
208 .m_reg = 0x0048,
209 .n_reg = 0x004c,
210 .config_reg = 0x0050,
211 .mode_reg = 0x0040,
212 .status_reg = 0x005c,
223 .enable_reg = 0x0100,
234 .l_reg = 0x4104,
235 .m_reg = 0x4108,
236 .n_reg = 0x410c,
237 .config_reg = 0x4110,
238 .mode_reg = 0x4100,
239 .status_reg = 0x411c,
249 .l_reg = 0x0084,
250 .m_reg = 0x0088,
251 .n_reg = 0x008c,
252 .config_reg = 0x0090,
253 .mode_reg = 0x0080,
254 .status_reg = 0x009c,
265 .cmd_rcgr = 0x5000,
277 F( 19200000, P_XO, 1, 0, 0),
278 F( 37500000, P_GPLL0, 16, 0, 0),
279 F( 50000000, P_GPLL0, 12, 0, 0),
280 F( 75000000, P_GPLL0, 8, 0, 0),
281 F(100000000, P_GPLL0, 6, 0, 0),
282 F(150000000, P_GPLL0, 4, 0, 0),
283 F(291750000, P_MMPLL1, 4, 0, 0),
284 F(400000000, P_MMPLL0, 2, 0, 0),
285 F(466800000, P_MMPLL1, 2.5, 0, 0),
289 .cmd_rcgr = 0x5040,
302 F( 19200000, P_XO, 1, 0, 0),
303 F( 37500000, P_GPLL0, 16, 0, 0),
304 F( 50000000, P_GPLL0, 12, 0, 0),
305 F( 75000000, P_GPLL0, 8, 0, 0),
306 F(100000000, P_GPLL0, 6, 0, 0),
307 F(150000000, P_GPLL0, 4, 0, 0),
308 F(291750000, P_MMPLL1, 4, 0, 0),
309 F(400000000, P_MMPLL0, 2, 0, 0),
313 .cmd_rcgr = 0x5090,
326 F(100000000, P_GPLL0, 6, 0, 0),
327 F(200000000, P_MMPLL0, 4, 0, 0),
332 .cmd_rcgr = 0x3090,
345 .cmd_rcgr = 0x3100,
358 .cmd_rcgr = 0x3160,
371 .cmd_rcgr = 0x31c0,
384 F(37500000, P_GPLL0, 16, 0, 0),
385 F(50000000, P_GPLL0, 12, 0, 0),
386 F(60000000, P_GPLL0, 10, 0, 0),
387 F(80000000, P_GPLL0, 7.5, 0, 0),
388 F(100000000, P_GPLL0, 6, 0, 0),
389 F(109090000, P_GPLL0, 5.5, 0, 0),
390 F(133330000, P_GPLL0, 4.5, 0, 0),
391 F(200000000, P_GPLL0, 3, 0, 0),
392 F(228570000, P_MMPLL0, 3.5, 0, 0),
393 F(266670000, P_MMPLL0, 3, 0, 0),
394 F(320000000, P_MMPLL0, 2.5, 0, 0),
395 F(400000000, P_MMPLL0, 2, 0, 0),
396 F(465000000, P_MMPLL3, 2, 0, 0),
401 .cmd_rcgr = 0x3600,
414 .cmd_rcgr = 0x3620,
427 F(37500000, P_GPLL0, 16, 0, 0),
428 F(60000000, P_GPLL0, 10, 0, 0),
429 F(75000000, P_GPLL0, 8, 0, 0),
430 F(85710000, P_GPLL0, 7, 0, 0),
431 F(100000000, P_GPLL0, 6, 0, 0),
432 F(133330000, P_MMPLL0, 6, 0, 0),
433 F(160000000, P_MMPLL0, 5, 0, 0),
434 F(200000000, P_MMPLL0, 4, 0, 0),
435 F(228570000, P_MMPLL0, 3.5, 0, 0),
436 F(240000000, P_GPLL0, 2.5, 0, 0),
437 F(266670000, P_MMPLL0, 3, 0, 0),
438 F(320000000, P_MMPLL0, 2.5, 0, 0),
443 .cmd_rcgr = 0x2040,
456 F(75000000, P_GPLL0, 8, 0, 0),
457 F(133330000, P_GPLL0, 4.5, 0, 0),
458 F(200000000, P_GPLL0, 3, 0, 0),
459 F(228570000, P_MMPLL0, 3.5, 0, 0),
460 F(266670000, P_MMPLL0, 3, 0, 0),
461 F(320000000, P_MMPLL0, 2.5, 0, 0),
466 .cmd_rcgr = 0x3500,
479 .cmd_rcgr = 0x3520,
492 .cmd_rcgr = 0x3540,
505 .cmd_rcgr = 0x2000,
519 .cmd_rcgr = 0x2020,
533 F(50000000, P_GPLL0, 12, 0, 0),
534 F(100000000, P_GPLL0, 6, 0, 0),
535 F(133330000, P_MMPLL0, 6, 0, 0),
536 F(200000000, P_MMPLL0, 4, 0, 0),
537 F(266670000, P_MMPLL0, 3, 0, 0),
538 F(465000000, P_MMPLL3, 2, 0, 0),
543 .cmd_rcgr = 0x1000,
557 F(19200000, P_XO, 1, 0, 0),
562 .cmd_rcgr = 0x3300,
585 .cmd_rcgr = 0x3420,
599 .cmd_rcgr = 0x3450,
613 F(4800000, P_XO, 4, 0, 0),
616 F(9600000, P_XO, 2, 0, 0),
618 F(19200000, P_XO, 1, 0, 0),
621 F(48000000, P_GPLL0, 12.5, 0, 0),
622 F(64000000, P_MMPLL0, 12.5, 0, 0),
623 F(66670000, P_GPLL0, 9, 0, 0),
628 .cmd_rcgr = 0x3360,
641 .cmd_rcgr = 0x3390,
654 .cmd_rcgr = 0x33c0,
667 .cmd_rcgr = 0x33f0,
680 F(100000000, P_GPLL0, 6, 0, 0),
681 F(200000000, P_MMPLL0, 4, 0, 0),
686 .cmd_rcgr = 0x3000,
699 .cmd_rcgr = 0x3030,
712 .cmd_rcgr = 0x3060,
725 F(133330000, P_GPLL0, 4.5, 0, 0),
726 F(266670000, P_MMPLL0, 3, 0, 0),
727 F(320000000, P_MMPLL0, 2.5, 0, 0),
728 F(400000000, P_MMPLL0, 2, 0, 0),
729 F(465000000, P_MMPLL3, 2, 0, 0),
734 .cmd_rcgr = 0x3640,
752 .cmd_rcgr = 0x2120,
766 .cmd_rcgr = 0x2140,
780 F(19200000, P_XO, 1, 0, 0),
785 .cmd_rcgr = 0x20e0,
798 F(135000000, P_EDPLINK, 2, 0, 0),
799 F(270000000, P_EDPLINK, 11, 0, 0),
804 .cmd_rcgr = 0x20c0,
823 .cmd_rcgr = 0x20a0,
837 F(19200000, P_XO, 1, 0, 0),
842 .cmd_rcgr = 0x2160,
855 .cmd_rcgr = 0x2180,
873 .cmd_rcgr = 0x2060,
887 F(19200000, P_XO, 1, 0, 0),
892 .cmd_rcgr = 0x2100,
905 F(19200000, P_XO, 1, 0, 0),
910 .cmd_rcgr = 0x2080,
923 .halt_reg = 0x3348,
925 .enable_reg = 0x3348,
926 .enable_mask = BIT(0),
939 .halt_reg = 0x3344,
941 .enable_reg = 0x3344,
942 .enable_mask = BIT(0),
956 .halt_reg = 0x30bc,
958 .enable_reg = 0x30bc,
959 .enable_mask = BIT(0),
972 .halt_reg = 0x30b4,
974 .enable_reg = 0x30b4,
975 .enable_mask = BIT(0),
989 .halt_reg = 0x30c4,
991 .enable_reg = 0x30c4,
992 .enable_mask = BIT(0),
1006 .halt_reg = 0x30e4,
1008 .enable_reg = 0x30e4,
1009 .enable_mask = BIT(0),
1023 .halt_reg = 0x30d4,
1025 .enable_reg = 0x30d4,
1026 .enable_mask = BIT(0),
1040 .halt_reg = 0x3128,
1042 .enable_reg = 0x3128,
1043 .enable_mask = BIT(0),
1056 .halt_reg = 0x3124,
1058 .enable_reg = 0x3124,
1059 .enable_mask = BIT(0),
1073 .halt_reg = 0x3134,
1075 .enable_reg = 0x3134,
1076 .enable_mask = BIT(0),
1090 .halt_reg = 0x3154,
1092 .enable_reg = 0x3154,
1093 .enable_mask = BIT(0),
1107 .halt_reg = 0x3144,
1109 .enable_reg = 0x3144,
1110 .enable_mask = BIT(0),
1124 .halt_reg = 0x3188,
1126 .enable_reg = 0x3188,
1127 .enable_mask = BIT(0),
1140 .halt_reg = 0x3184,
1142 .enable_reg = 0x3184,
1143 .enable_mask = BIT(0),
1157 .halt_reg = 0x3194,
1159 .enable_reg = 0x3194,
1160 .enable_mask = BIT(0),
1174 .halt_reg = 0x31b4,
1176 .enable_reg = 0x31b4,
1177 .enable_mask = BIT(0),
1191 .halt_reg = 0x31a4,
1193 .enable_reg = 0x31a4,
1194 .enable_mask = BIT(0),
1208 .halt_reg = 0x31e8,
1210 .enable_reg = 0x31e8,
1211 .enable_mask = BIT(0),
1224 .halt_reg = 0x31e4,
1226 .enable_reg = 0x31e4,
1227 .enable_mask = BIT(0),
1241 .halt_reg = 0x31f4,
1243 .enable_reg = 0x31f4,
1244 .enable_mask = BIT(0),
1258 .halt_reg = 0x3214,
1260 .enable_reg = 0x3214,
1261 .enable_mask = BIT(0),
1275 .halt_reg = 0x3204,
1277 .enable_reg = 0x3204,
1278 .enable_mask = BIT(0),
1292 .halt_reg = 0x3704,
1294 .enable_reg = 0x3704,
1295 .enable_mask = BIT(0),
1309 .halt_reg = 0x3714,
1311 .enable_reg = 0x3714,
1312 .enable_mask = BIT(0),
1326 .halt_reg = 0x3444,
1328 .enable_reg = 0x3444,
1329 .enable_mask = BIT(0),
1343 .halt_reg = 0x3474,
1345 .enable_reg = 0x3474,
1346 .enable_mask = BIT(0),
1360 .halt_reg = 0x3224,
1362 .enable_reg = 0x3224,
1363 .enable_mask = BIT(0),
1376 .halt_reg = 0x35a8,
1378 .enable_reg = 0x35a8,
1379 .enable_mask = BIT(0),
1393 .halt_reg = 0x35ac,
1395 .enable_reg = 0x35ac,
1396 .enable_mask = BIT(0),
1410 .halt_reg = 0x35b0,
1412 .enable_reg = 0x35b0,
1413 .enable_mask = BIT(0),
1427 .halt_reg = 0x35b4,
1429 .enable_reg = 0x35b4,
1430 .enable_mask = BIT(0),
1443 .halt_reg = 0x35b8,
1445 .enable_reg = 0x35b8,
1446 .enable_mask = BIT(0),
1459 .halt_reg = 0x35bc,
1461 .enable_reg = 0x35bc,
1462 .enable_mask = BIT(0),
1476 .halt_reg = 0x3384,
1478 .enable_reg = 0x3384,
1479 .enable_mask = BIT(0),
1493 .halt_reg = 0x33b4,
1495 .enable_reg = 0x33b4,
1496 .enable_mask = BIT(0),
1510 .halt_reg = 0x33e4,
1512 .enable_reg = 0x33e4,
1513 .enable_mask = BIT(0),
1527 .halt_reg = 0x3414,
1529 .enable_reg = 0x3414,
1530 .enable_mask = BIT(0),
1544 .halt_reg = 0x3494,
1546 .enable_reg = 0x3494,
1547 .enable_mask = BIT(0),
1560 .halt_reg = 0x3024,
1562 .enable_reg = 0x3024,
1563 .enable_mask = BIT(0),
1577 .halt_reg = 0x3054,
1579 .enable_reg = 0x3054,
1580 .enable_mask = BIT(0),
1594 .halt_reg = 0x3084,
1596 .enable_reg = 0x3084,
1597 .enable_mask = BIT(0),
1611 .halt_reg = 0x3484,
1613 .enable_reg = 0x3484,
1614 .enable_mask = BIT(0),
1627 .halt_reg = 0x36b4,
1629 .enable_reg = 0x36b4,
1630 .enable_mask = BIT(0),
1643 .halt_reg = 0x36b0,
1645 .enable_reg = 0x36b0,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x36a8,
1662 .enable_reg = 0x36a8,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x36ac,
1679 .enable_reg = 0x36ac,
1680 .enable_mask = BIT(0),
1694 .halt_reg = 0x36b8,
1696 .enable_reg = 0x36b8,
1697 .enable_mask = BIT(0),
1710 .halt_reg = 0x36bc,
1712 .enable_reg = 0x36bc,
1713 .enable_mask = BIT(0),
1726 .halt_reg = 0x36c0,
1728 .enable_reg = 0x36c0,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x2308,
1745 .enable_reg = 0x2308,
1746 .enable_mask = BIT(0),
1759 .halt_reg = 0x2310,
1761 .enable_reg = 0x2310,
1762 .enable_mask = BIT(0),
1776 .halt_reg = 0x233c,
1778 .enable_reg = 0x233c,
1779 .enable_mask = BIT(0),
1793 .halt_reg = 0x2340,
1795 .enable_reg = 0x2340,
1796 .enable_mask = BIT(0),
1810 .halt_reg = 0x2334,
1812 .enable_reg = 0x2334,
1813 .enable_mask = BIT(0),
1827 .halt_reg = 0x2330,
1829 .enable_reg = 0x2330,
1830 .enable_mask = BIT(0),
1844 .halt_reg = 0x232c,
1846 .enable_reg = 0x232c,
1847 .enable_mask = BIT(0),
1861 .halt_reg = 0x2344,
1863 .enable_reg = 0x2344,
1864 .enable_mask = BIT(0),
1878 .halt_reg = 0x2348,
1880 .enable_reg = 0x2348,
1881 .enable_mask = BIT(0),
1895 .halt_reg = 0x2324,
1897 .enable_reg = 0x2324,
1898 .enable_mask = BIT(0),
1912 .halt_reg = 0x230c,
1914 .enable_reg = 0x230c,
1915 .enable_mask = BIT(0),
1928 .halt_reg = 0x2338,
1930 .enable_reg = 0x2338,
1931 .enable_mask = BIT(0),
1945 .halt_reg = 0x231c,
1947 .enable_reg = 0x231c,
1948 .enable_mask = BIT(0),
1962 .halt_reg = 0x2320,
1964 .enable_reg = 0x2320,
1965 .enable_mask = BIT(0),
1979 .halt_reg = 0x2314,
1981 .enable_reg = 0x2314,
1982 .enable_mask = BIT(0),
1996 .halt_reg = 0x2318,
1998 .enable_reg = 0x2318,
1999 .enable_mask = BIT(0),
2013 .halt_reg = 0x2328,
2015 .enable_reg = 0x2328,
2016 .enable_mask = BIT(0),
2030 .halt_reg = 0x502c,
2032 .enable_reg = 0x502c,
2033 .enable_mask = BIT(0),
2046 .halt_reg = 0x5024,
2048 .enable_reg = 0x5024,
2049 .enable_mask = BIT(0),
2063 .halt_reg = 0x5028,
2065 .enable_reg = 0x5028,
2066 .enable_mask = BIT(0),
2080 .halt_reg = 0x506c,
2082 .enable_reg = 0x506c,
2083 .enable_mask = BIT(0),
2097 .halt_reg = 0x5064,
2099 .enable_reg = 0x5064,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x405c,
2116 .enable_reg = 0x405c,
2117 .enable_mask = BIT(0),
2130 .halt_reg = 0x4058,
2132 .enable_reg = 0x4058,
2133 .enable_mask = BIT(0),
2147 .halt_reg = 0x402c,
2149 .enable_reg = 0x402c,
2150 .enable_mask = BIT(0),
2164 .halt_reg = 0x50b4,
2166 .enable_reg = 0x50b4,
2167 .enable_mask = BIT(0),
2181 .halt_reg = 0x4028,
2183 .enable_reg = 0x4028,
2184 .enable_mask = BIT(0),
2198 .halt_reg = 0x403c,
2200 .enable_reg = 0x403c,
2201 .enable_mask = BIT(0),
2214 .halt_reg = 0x4038,
2216 .enable_reg = 0x4038,
2217 .enable_mask = BIT(0),
2230 .halt_reg = 0x1030,
2232 .enable_reg = 0x1030,
2233 .enable_mask = BIT(0),
2246 .halt_reg = 0x1034,
2248 .enable_reg = 0x1034,
2249 .enable_mask = BIT(0),
2262 .halt_reg = 0x1038,
2264 .enable_reg = 0x1038,
2265 .enable_mask = BIT(0),
2279 .halt_reg = 0x1028,
2281 .enable_reg = 0x1028,
2282 .enable_mask = BIT(0),
2299 .vco_val = 0x0,
2300 .vco_mask = 0x3 << 20,
2301 .pre_div_val = 0x0,
2302 .pre_div_mask = 0x7 << 12,
2303 .post_div_val = 0x0,
2304 .post_div_mask = 0x3 << 8,
2306 .main_output_mask = BIT(0),
2313 .vco_val = 0x0,
2314 .vco_mask = 0x3 << 20,
2315 .pre_div_val = 0x0,
2316 .pre_div_mask = 0x7 << 12,
2317 .post_div_val = 0x0,
2318 .post_div_mask = 0x3 << 8,
2320 .main_output_mask = BIT(0),
2325 .gdscr = 0x1024,
2326 .cxcs = (unsigned int []){ 0x1028 },
2337 .gdscr = 0x2304,
2338 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2347 .gdscr = 0x35a4,
2348 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2357 .gdscr = 0x36a4,
2358 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2367 .gdscr = 0x4024,
2368 .cxcs = (unsigned int []){ 0x4028 },
2377 .gdscr = 0x4034,
2514 [SPDM_RESET] = { 0x0200 },
2515 [SPDM_RM_RESET] = { 0x0300 },
2516 [VENUS0_RESET] = { 0x1020 },
2517 [MDSS_RESET] = { 0x2300 },
2518 [CAMSS_PHY0_RESET] = { 0x3020 },
2519 [CAMSS_PHY1_RESET] = { 0x3050 },
2520 [CAMSS_PHY2_RESET] = { 0x3080 },
2521 [CAMSS_CSI0_RESET] = { 0x30b0 },
2522 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2523 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2524 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2525 [CAMSS_CSI1_RESET] = { 0x3120 },
2526 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2527 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2528 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2529 [CAMSS_CSI2_RESET] = { 0x3180 },
2530 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2531 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2532 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2533 [CAMSS_CSI3_RESET] = { 0x31e0 },
2534 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2535 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2536 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2537 [CAMSS_ISPIF_RESET] = { 0x3220 },
2538 [CAMSS_CCI_RESET] = { 0x3340 },
2539 [CAMSS_MCLK0_RESET] = { 0x3380 },
2540 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2541 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2542 [CAMSS_MCLK3_RESET] = { 0x3410 },
2543 [CAMSS_GP0_RESET] = { 0x3440 },
2544 [CAMSS_GP1_RESET] = { 0x3470 },
2545 [CAMSS_TOP_RESET] = { 0x3480 },
2546 [CAMSS_MICRO_RESET] = { 0x3490 },
2547 [CAMSS_JPEG_RESET] = { 0x35a0 },
2548 [CAMSS_VFE_RESET] = { 0x36a0 },
2549 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2550 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2551 [OXILI_RESET] = { 0x4020 },
2552 [OXILICX_RESET] = { 0x4030 },
2553 [OCMEMCX_RESET] = { 0x4050 },
2554 [MMSS_RBCRP_RESET] = { 0x4080 },
2555 [MMSSNOCAHB_RESET] = { 0x5020 },
2556 [MMSSNOCAXI_RESET] = { 0x5060 },
2557 [OCMEMNOC_RESET] = { 0x50b0 },
2573 .max_register = 0x5104,