Lines Matching +full:parent +full:- +full:clock +full:- +full:frequency

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Common Clock Framework support for all PLL's in Samsung platforms
15  * @prate: frequency of the primary parent clock (in KHz).
20  * clock domain. The parent frequency at which these divider values are valid is
21  * specified in @prate. The @prate is the frequency of the primary parent clock.
22  * For CPU clock domains that do not have a DIV1 register, the @div1 member
32  * struct exynos_cpuclk: information about clock supplied to a CPU core.
33  * @hw:	handle between CCF and CPU clock.
34  * @alt_parent: alternate parent clock to use when switching the speed
35  *	of the primary parent clock.
36  * @ctrl_base:	base address of the clock controller.
37  * @lock: cpu clock domain register access lock.
38  * @cfg: cpu clock rate configuration data.
40  * @clk_nb: clock notifier registered for changes in clock speed of the
41  *	primary parent clock.
42  * @flags: configuration flags for the CPU clock.
44  * This structure holds information required for programming the CPU clock for
45  * various clock speeds.
57 /* The CPU clock registers have DIV1 configuration register */
59 /* When ALT parent is active, debug clocks need safe divider values */
61 /* The CPU clock registers have Exynos5433-compatible layout */
67 			const struct clk_hw *parent, const struct clk_hw *alt_parent,