1 // SPDX-License-Identifier:	GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
38 	unsigned long arefdiv, reg, mdiv;  in agilex_clk_pll_recalc_rate()  local
41 	/* read VCO1 reg for numerator and denominator */  in agilex_clk_pll_recalc_rate()
42 	reg = readl(socfpgaclk->hw.reg);  in agilex_clk_pll_recalc_rate()
43 	arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;  in agilex_clk_pll_recalc_rate()
48 	reg = readl(socfpgaclk->hw.reg + 0x24);  in agilex_clk_pll_recalc_rate()
49 	mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK;  in agilex_clk_pll_recalc_rate()
61 	unsigned long reg;  in clk_pll_recalc_rate()  local
64 	/* read VCO1 reg for numerator and denominator */  in clk_pll_recalc_rate()
65 	reg = readl(socfpgaclk->hw.reg);  in clk_pll_recalc_rate()
66 	refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;  in clk_pll_recalc_rate()
72 	reg = readl(socfpgaclk->hw.reg + 0x4);  in clk_pll_recalc_rate()
73 	mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;  in clk_pll_recalc_rate()
85 	div = ((readl(socfpgaclk->hw.reg) &  in clk_boot_clk_recalc_rate()
98 	pll_src = readl(socfpgaclk->hw.reg);  in clk_pll_get_parent()
108 	pll_src = readl(socfpgaclk->hw.reg);  in clk_boot_get_parent()
116 	u32 reg;  in clk_pll_prepare()  local
119 	reg = readl(socfpgaclk->hw.reg);  in clk_pll_prepare()
120 	reg |= SOCFPGA_PLL_RESET_MASK;  in clk_pll_prepare()
121 	writel(reg, socfpgaclk->hw.reg);  in clk_pll_prepare()
145 			     void __iomem *reg)  in s10_register_pll()  argument
149 	struct clk_init_data init;  in s10_register_pll()  local
150 	const char *name = clks->name;  in s10_register_pll()
156 	pll_clk->hw.reg = reg + clks->offset;  in s10_register_pll()
159 		init.ops = &clk_boot_ops;  in s10_register_pll()
161 		init.ops = &clk_pll_ops;  in s10_register_pll()
163 	init.name = name;  in s10_register_pll()
164 	init.flags = clks->flags;  in s10_register_pll()
166 	init.num_parents = clks->num_parents;  in s10_register_pll()
167 	init.parent_names = NULL;  in s10_register_pll()
168 	init.parent_data = clks->parent_data;  in s10_register_pll()
169 	pll_clk->hw.hw.init = &init;  in s10_register_pll()
171 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;  in s10_register_pll()
173 	clk = clk_register(NULL, &pll_clk->hw.hw);  in s10_register_pll()
182 				void __iomem *reg)  in agilex_register_pll()  argument
186 	struct clk_init_data init;  in agilex_register_pll()  local
187 	const char *name = clks->name;  in agilex_register_pll()
193 	pll_clk->hw.reg = reg + clks->offset;  in agilex_register_pll()
196 		init.ops = &clk_boot_ops;  in agilex_register_pll()
198 		init.ops = &agilex_clk_pll_ops;  in agilex_register_pll()
200 	init.name = name;  in agilex_register_pll()
201 	init.flags = clks->flags;  in agilex_register_pll()
203 	init.num_parents = clks->num_parents;  in agilex_register_pll()
204 	init.parent_names = NULL;  in agilex_register_pll()
205 	init.parent_data = clks->parent_data;  in agilex_register_pll()
206 	pll_clk->hw.hw.init = &init;  in agilex_register_pll()
208 	pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;  in agilex_register_pll()
210 	clk = clk_register(NULL, &pll_clk->hw.hw);  in agilex_register_pll()