44 	struct dpll_data *ad;  in dra7_apll_enable()  local
49 	ad = clk->dpll_data;  in dra7_apll_enable()
50 	if (!ad)  in dra7_apll_enable()
55 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
58 	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
60 	if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
63 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_enable()
64 	v &= ~ad->enable_mask;  in dra7_apll_enable()
65 	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);  in dra7_apll_enable()
66 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_enable()
68 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
71 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
72 		if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
94 	struct dpll_data *ad;  in dra7_apll_disable()  local
98 	ad = clk->dpll_data;  in dra7_apll_disable()
100 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_disable()
102 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_disable()
103 	v &= ~ad->enable_mask;  in dra7_apll_disable()
104 	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);  in dra7_apll_disable()
105 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_disable()
111 	struct dpll_data *ad;  in dra7_apll_is_enabled()  local
114 	ad = clk->dpll_data;  in dra7_apll_is_enabled()
116 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_is_enabled()
117 	v &= ad->enable_mask;  in dra7_apll_is_enabled()
119 	v >>= __ffs(ad->enable_mask);  in dra7_apll_is_enabled()
141 	struct dpll_data *ad = clk_hw->dpll_data;  in omap_clk_register_apll()  local
156 	ad->clk_ref = __clk_get_hw(clk);  in omap_clk_register_apll()
168 	ad->clk_bypass = __clk_get_hw(clk);  in omap_clk_register_apll()
188 	struct dpll_data *ad = NULL;  in of_dra7_apll_setup()  local
194 	ad = kzalloc(sizeof(*ad), GFP_KERNEL);  in of_dra7_apll_setup()
197 	if (!ad || !clk_hw || !init)  in of_dra7_apll_setup()
200 	clk_hw->dpll_data = ad;  in of_dra7_apll_setup()
220 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_dra7_apll_setup()
221 	ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);  in of_dra7_apll_setup()
226 	ad->idlest_mask = 0x1;  in of_dra7_apll_setup()
227 	ad->enable_mask = 0x3;  in of_dra7_apll_setup()
234 	kfree(ad);  in of_dra7_apll_setup()
246 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_is_enabled()  local
249 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_is_enabled()
250 	v &= ad->enable_mask;  in omap2_apll_is_enabled()
252 	v >>= __ffs(ad->enable_mask);  in omap2_apll_is_enabled()
271 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_enable()  local
275 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_enable()
276 	v &= ~ad->enable_mask;  in omap2_apll_enable()
277 	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);  in omap2_apll_enable()
278 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_enable()
281 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in omap2_apll_enable()
282 		if (v & ad->idlest_mask)  in omap2_apll_enable()
302 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_disable()  local
305 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_disable()
306 	v &= ~ad->enable_mask;  in omap2_apll_disable()
307 	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);  in omap2_apll_disable()
308 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_disable()
320 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_set_autoidle()  local
323 	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);  in omap2_apll_set_autoidle()
324 	v &= ~ad->autoidle_mask;  in omap2_apll_set_autoidle()
325 	v |= val << __ffs(ad->autoidle_mask);  in omap2_apll_set_autoidle()
326 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_set_autoidle()
349 	struct dpll_data *ad = NULL;  in of_omap2_apll_setup()  local
358 	ad = kzalloc(sizeof(*ad), GFP_KERNEL);  in of_omap2_apll_setup()
362 	if (!ad || !clk_hw || !init)  in of_omap2_apll_setup()
365 	clk_hw->dpll_data = ad;  in of_omap2_apll_setup()
393 	ad->enable_mask = 0x3 << val;  in of_omap2_apll_setup()
394 	ad->autoidle_mask = 0x3 << val;  in of_omap2_apll_setup()
401 	ad->idlest_mask = 1 << val;  in of_omap2_apll_setup()
403 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_omap2_apll_setup()
404 	ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);  in of_omap2_apll_setup()
405 	ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);  in of_omap2_apll_setup()
418 	kfree(ad);  in of_omap2_apll_setup()